An Automated Dna Strands Detection System Featuring 32-Bit Arm7tdmi Microcontroller And Vga-Cmos Digital Image Sensor.

Genetic DNA recognition is a routine experiment for detecting the origin of the species. Electrophoresis is one of the processes for such detection which has been used extensively. Pengecaman genetik DNA ialah eksperimen rutin untuk mengesan asal usul sesuatu spesis. Proses electrophoresis ialah salah satu proses pengecaman yang digunakan secara meluas

SCREAM: Sensory Channel Remote Execution Attack Methods

Sensory channel threats on embedded systems are an often overlooked attack vector. Because many computing systems focus on digital communication, much of the security research for embedded systems has focused on securing the communication channels between devices. This project explores sensory channel attack concepts and demonstrates that an attack on an embedded device purely through sensory channel inputs can achieve arbitrary code execution. Unlike previous research on sensory channel attacks, this work does not require the device to have preloaded malware. We demonstrate that our attacks were successful in two separate, realistic applications with up to a 100.00% success rate. Finally, we propose a possible defense to these attacks and suggest future avenues of research in this field

DIEstro: Motion sensor platform for cattle oestrus detection

The reproductive efficiency of dairy industry has decreased over the last ten years due mainly to an intensification of the management techniques of the herd, and an increase of total number of animals. A main objective of worldwide dairy farms is to ensure that dairy cows, produce as much milk as possible. A cow produces milk while it has a calf to breastfeed, therefore, the less time passes between births, the more ”productive” the cows are. This is the principal reason why the precise heat (oestrus) detection has became so important, a task traditionally assigned to veterinary and expert people examining and watching the cattle behavior, and in recent years to electronic devices monitoring the cow’s physical activity. Tracking the animal’s physical activity by means of a portable device strapped to each animal, is known to be a very effective way to determine heat, but sometimes requires expensive hardware and large batteries. In this work, a low-cost micropower wireless system able to automatically detect oestrus period of cattle is presented. It was designed in cooperation with BQN, a company developing technology for the agribusiness industry in Uruguay. The tracker seizes the recent availability of 1 uA micropower accelerometers, LoRa long range transceivers, and FRAM microcontrollers, to achieve a coin cell battery powered paradigm for oestrus detection. The device records 3 axis acceleration information, process it, and periodically sends it to a server; it has a measured ultra low power consumption of 4 uA while collecting/processing data, reaching a very large (> 10km) communication distance using a star topology and LoRa technology at countryside areas. The scope of the project and this documentation is the entire hardware and firmware development, from the start idea, design and final implementation.Agencia Nacional de Investigación e Innovació

DIEstro: Motion sensor platform for cattle oestrus detection

The reproductive efficiency of dairy industry has decreased over the last ten years due mainly to an intensification of the management techniques of the herd, and an increase of total number of animals. A main objective of worldwide dairy farms is to ensure that dairy cows, produce as much milk as possible. A cow produces milk while it has a calf to breastfeed, therefore, the less time passes between births, the more ”productive” the cows are. This is the principal reason why the precise heat (oestrus) detection has became so important, a task traditionally assigned to veterinary and expert people examining and watching the cattle behavior, and in recent years to electronic devices monitoring the cow’s physical activity. Tracking the animal’s physical activity by means of a portable device strapped to each animal, is known to be a very effective way to determine heat, but sometimes requires expensive hardware and large batteries. In this work, a low-cost micropower wireless system able to automatically detect oestrus period of cattle is presented. It was designed in cooperation with BQN, a company developing technology for the agribusiness industry in Uruguay. The tracker seizes the recent availability of 1 uA micropower accelerometers, LoRa long range transceivers, and FRAM microcontrollers, to achieve a coin cell battery powered paradigm for oestrus detection. The device records 3 axis acceleration information, process it, and periodically sends it to a server; it has a measured ultra low power consumption of 4 uA while collecting/processing data, reaching a very large (> 10km) communication distance using a star topology and LoRa technology at countryside areas. The scope of the project and this documentation is the entire hardware and firmware development, from the start idea, design and final implementation.Agencia Nacional de Investigación e Innovació

Transiently Powered Computers

Demand for compact, easily deployable, energy-efficient computers has driven the development of general-purpose transiently powered computers (TPCs) that lack both batteries and wired power, operating exclusively on energy harvested from their surroundings. TPCs\u27 dependence solely on transient, harvested power offers several important design-time benefits. For example, omitting batteries saves board space and weight while obviating the need to make devices physically accessible for maintenance. However, transient power may provide an unpredictable supply of energy that makes operation difficult. A predictable energy supply is a key abstraction underlying most electronic designs. TPCs discard this abstraction in favor of opportunistic computation that takes advantage of available resources. A crucial question is how should a software-controlled computing device operate if it depends completely on external entities for power and other resources? The question poses challenges for computation, communication, storage, and other aspects of TPC design. The main idea of this work is that software techniques can make energy harvesting a practicable form of power supply for electronic devices. Its overarching goal is to facilitate the design and operation of usable TPCs. This thesis poses a set of challenges that are fundamental to TPCs, then pairs these challenges with approaches that use software techniques to address them. To address the challenge of computing steadily on harvested power, it describes Mementos, an energy-aware state-checkpointing system for TPCs. To address the dependence of opportunistic RF-harvesting TPCs on potentially untrustworthy RFID readers, it describes CCCP, a protocol and system for safely outsourcing data storage to RFID readers that may attempt to tamper with data. Additionally, it describes a simulator that facilitates experimentation with the TPC model, and a prototype computational RFID that implements the TPC model. To show that TPCs can improve existing electronic devices, this thesis describes applications of TPCs to implantable medical devices (IMDs), a challenging design space in which some battery-constrained devices completely lack protection against radio-based attacks. TPCs can provide security and privacy benefits to IMDs by, for instance, cryptographically authenticating other devices that want to communicate with the IMD before allowing the IMD to use any of its battery power. This thesis describes a simplified IMD that lacks its own radio, saving precious battery energy and therefore size. The simplified IMD instead depends on an RFID-scale TPC for all of its communication functions. TPCs are a natural area of exploration for future electronic design, given the parallel trends of energy harvesting and miniaturization. This work aims to establish and evaluate basic principles by which TPCs can operate

Investigation of Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time

This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error

Dynamically reconfigurable architecture for embedded computer vision systems

The objective of this research work is to design, develop and implement a new architecture which integrates on the same chip all the processing levels of a complete Computer Vision system, so that the execution is efficient without compromising the power consumption while keeping a reduced cost. For this purpose, an analysis and classification of different mathematical operations and algorithms commonly used in Computer Vision are carried out, as well as a in-depth review of the image processing capabilities of current-generation hardware devices. This permits to determine the requirements and the key aspects for an efficient architecture. A representative set of algorithms is employed as benchmark to evaluate the proposed architecture, which is implemented on an FPGA-based system-on-chip. Finally, the prototype is compared to other related approaches in order to determine its advantages and weaknesses

Developing silicon pixel detectors for LHCb: constructing the VELO Upgrade and developing a MAPS-based tracking detector

The Large Hadron Collider beauty (LHCb) experiment is currently undergoing a major upgrade of its detector, including the construction of a new silicon pixel detector, the Vertex Locator (VELO) Upgrade. The challenges faced by the LHCb VELO Upgrade are discussed, and the design to overcome them is presented. VELO modules have been produced at the University of Manchester. The VELO modules use 55 $\mu$m pixels operating 5.1 mm from the beam without a beam pipe, an innovative silicon microchannel cooling substrate, and 40 MHz readout with a full detector bandwidth of 3 Tb/s. The module assembly process and the results of the associated R&D are presented. The mechanical and electronic tests are described. A grading scheme for each test is described, and the results are presented. The majority of the modules are of excellent quality, with 40 out of 43 of suitable quality for installation in the experiment. A full set of modules for the experiment has now been produced. The VELO Upgrade is read out into a data acquisition system based on an FPGA board. The architecture of the readout firmware for the readout FPGA for the VELO Upgrade is presented, and the function of each block described. Challenges arise due to the design of the VeloPix front end chip, the fully-software trigger and real-time analysis paradigm. These challenges are discussed and their solutions briefly described. An algorithm for identifying isolated clusters is presented and previously-considered approaches discussed. The current design uses around 83 % of the available logic blocks, and 85 % of the available memory blocks. A complete version of the firmware is now available and is being refined. An ultimate version of the LHCb experiment, the LHCb Upgrade II, is being designed for the 2030s to fully exploit the potential of the high luminosity LHC. The Mighty Tracker is the proposed new combined-technology downstream tracker for Upgrade II, consisting of a silicon pixel inner region and a scintillating fibre outer region. A potential layout of the detector and modules is given. The silicon pixels will likely be the first LHC tracker based on radiation-hard HV-MAPS technology. Studies for the electronic readout system of the silicon inner region are reported. The total bandwidth and its distribution across the tracker are discussed. The numbers of key readout and FPGA DAQ boards are calculated. The detector's expected data rate is 8.13 Tb/s in Upgrade II conditions over a total of more than 46,000 front end chips

PROPOSED MIDDLEWARE SOLUTION FOR RESOURCE-CONSTRAINED DISTRIBUTED EMBEDDED NETWORKS

The explosion in processing power of embedded systems has enabled distributed embedded networks to perform more complicated tasks. Middleware are sets of encapsulations of common and network/operating system-specific functionality into generic, reusable frameworks to manage such distributed networks. This thesis will survey and categorize popular middleware implementations into three adapted layers: host-infrastructure, distribution, and common services. This thesis will then apply a quantitative approach to grading and proposing a single middleware solution from all layers for two target platforms: CubeSats and autonomous unmanned aerial vehicles (UAVs). CubeSats are 10x10x10cm nanosatellites that are popular university-level space missions, and impose power and volume constraints. Autonomous UAVs are similarly-popular hobbyist-level vehicles that exhibit similar power and volume constraints. The MAVLink middleware from the host-infrastructure layer is proposed as the middleware to manage the distributed embedded networks powering these platforms in future projects. Finally, this thesis presents a performance analysis on MAVLink managing the ARM Cortex-M 32-bit processors that power the target platforms