Techniques to Improve the Efficiency of Data Transmission in Cable Networks

The cable television (CATV) networks, since their introduction in the late 1940s, have now become a crucial part of the broadcasting industry. To keep up with growing demands from the subscribers, cable networks nowadays not only provide television programs but also deliver two-way interactive services such as telephone, high-speed Internet and social TV features. A new standard for CATV networks is released every five to six years to satisfy the growing demands from the mass market. From this perspective, this thesis is concerned with three main aspects for the continuing development of cable networks: (i) efficient implementations of backward-compatibility functions from the old standard, (ii) addressing and providing solutions for technically-challenging issues in the current standard and, (iii) looking for prospective features that can be implemented in the future standard. Since 1997, five different versions of the digital CATV standard had been released in North America. A new standard often contains major improvements over the previous one. The latest version of the standard, namely DOCSIS 3.1 (released in late 2013), is packed with state-of-the-art technologies and allows approximately ten times the amount of traffic as compared to the previous standard, DOCSIS 3.0 (released in 2008). Backward-compatibility is a must-have function for cable networks. In particular, to facilitate the system migration from older standards to a newer one, the backward compatible functions in the old standards must remain in the newer-standard products. More importantly, to keep the implementation cost low, the inherited backward compatible functions must be redesigned by taking advantage of the latest technology and algorithms. To improve the backward-compatibility functions, the first contribution of the thesis focuses on redesigning the pulse shaping filter by exploiting infinite impulse response (IIR) filter structures as an alternative to the conventional finite impulse response (FIR) structures. Comprehensive comparisons show that more economical filters with better performance can be obtained by the proposed design algorithm, which considers a hybrid parameterization of the filter's transfer function in combination with a constraint on the pole radius to be less than 1. The second contribution of the thesis is a new fractional timing estimation algorithm based on peak detection by log-domain interpolation. When compared with the commonly-used timing detection method, which is based on parabolic interpolation, the proposed algorithm yields more accurate estimation with a comparable implementation cost. The third contribution of the thesis is a technique to estimate the multipath channel for DOCSIS 3.1 cable networks. DOCSIS 3.1 is markedly different from prior generations of CATV networks in that OFDM/OFDMA is employed to create a spectrally-efficient signal. In order to effectively demodulate such a signal, it is necessary to employ a demodulation circuit which involves estimation and tracking of the multipath channel. The estimation and tracking must be highly accurate because extremely dense constellations such as 4096-QAM and possibly 16384-QAM can be used in DOCSIS 3.1. The conventional OFDM channel estimators available in the literature either do not perform satisfactorily or are not suitable for the DOCSIS 3.1 channel. The novel channel estimation technique proposed in this thesis iteratively searches for parameters of the channel paths. The proposed technique not only substantially enhances the channel estimation accuracy, but also can, at no cost, accurately identify the delay of each echo in the system. The echo delay information is valuable for proactive maintenance of the network. The fourth contribution of this thesis is a novel scheme that allows OFDM transmission without the use of a cyclic prefix (CP). The structure of OFDM in the current DOCSIS 3.1 does not achieve the maximum throughput if the channel has multipath components. The multipath channel causes inter-symbol-interference (ISI), which is commonly mitigated by employing CP. The CP acts as a guard interval that, while successfully protecting the signal from ISI, reduces the transmission throughput. The problem becomes more severe for downstream direction, where the throughput of the entire system is determined by the user with the worst channel. To solve the problem, this thesis proposes major alterations to the current DOCSIS 3.1 OFDM/OFDMA structure. The alterations involve using a pair of Nyquist filters at the transceivers and an efficient time-domain equalizer (TEQ) at the receiver to reduce ISI down to a negligible level without the need of CP. Simulation results demonstrate that, by incorporating the proposed alterations to the DOCSIS 3.1 down-link channel, the system can achieve the maximum throughput over a wide range of multipath channel conditions

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Low-pass CMOS Sigma-Delta Converter

A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante. O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução. Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption

Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.

The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision of a trillion connected sensors in the next decade. However there are still many design challenges ahead to make these sensor nodes small,low-cost,secure,reliable and energy-efficient to name a few. Since the wireless nodes are expected to operate on a limited energy source or in some cases on harvested energy, the energy consumption of each building block is of prime importance to prolong the life of a sensor node. It has been found that the radio communication when active has been one of the highest power consuming modules on a sensor node. Low-energy protocols, e.g. processing the raw sensor data on-node, are more energy efficient for some applications as compared to transmitting the raw data over a wireless channel to a cloud server. In this thesis we explore signal processing techniques to realize a low power radio solution for wireless communication. Two prototype chips have been designed and their performance has been evaluated. The first prototype chip exploits compressed sensing for Ultra-Wide-Band (UWB) communication. UWB signals typically require a high ADC sampling rate in the receiver which results in high power consumption. Compressed sensing is demonstrated to relax the ADC sampling rate to save power. The second prototype chip exploits the sensitivity vs. power trade-off in a radio receiver to achieve iso-performance at lower power consumption and the time-varying wireless channel characteristics are used to adapt the sampling frequency of the receiver based on the SNR/Link quality of the communication channel, saving power, while maintaining the desired system performance. It is envisioned that embedded machine learning will play a key role in the integration of sensory data with prior knowledge for distributed intelligent sensing which might enable reduced wireless network traffic to a cloud server. A Near-Threshold hardware accelerator for arbitrary Bayesian network was designed for clique-tree message passing algorithm used for probabilistic inference. The hardware accelerator was benchmarked by the mid-size ALARM Bayesian network with total energy consumption of 76nJ for 250µS execution time.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107130/1/oukhan_1.pd

Doctor of Philosophy

dissertationWireless communications pervade all avenues of modern life. The rapid expansion of wireless services has increased the need for transmission schemes that are more spectrally efficient. Dynamic spectrum access (DSA) systems attempt to address this need by building a network where the spectrum is used opportunistically by all users based on local and regional measurements of its availability. One of the principal requirements in DSA systems is to initialize and maintain a control channel to link the nodes together. This should be done even before a complete spectral usage map is available. Additionally, with more users accessing the spectrum, it is important to maintain a stable link in the presence of significant interference in emergency first-responders, rescue, and defense applications. In this thesis, a new multicarrier spread spectrum (MC-SS) technique based on filter banks is presented. The new technique is called filter bank multicarrier spread spectrum (FB-MC-SS). A detailed theory of the underlying properties of this signal are given, with emphasis on the properties that lend themselves to synchronization at the receiver. Proposed algorithms for synchronization, channel estimation, and detection are implemented on a software-defined radio platform to complete an FB-MC-SS transceiver and to prove the practicality of the technique. FB-MC-SS is shown through physical experimentation to be significantly more robust to partial band interference compared to direct sequence spread spectrum. With a higher power interfering signal occupying 90% of its band, FB-MC-SS maintains a low bit error rate. Under the same interference conditions, DS-SS fails completely. This experimentation leads to a theoretical analysis that shows in a frequency selective channel with additive white noise, the FB-MC-SS system has performance that equals that obtained by a DS-SS system employing an optimal rake receiver. This thesis contains a detailed chapter on implementation and design, including lessons learned while prototyping the system. This is to assist future system designers to quickly gain proficiency in further development of this technology

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Minimization of Interchannel Interference E ects in Nyquist-WDM Systems

ABSTRACT: The need of increasing the capacity of current deployed optical networks to perform terabits transmissions has been driven to the development of superchannel systems, (principally based on Nyquist-WDM) to be carried out in flexible grid or gridless scenarios. Nevertheless, one of the main issues to be mitigated in these systems is the interchannel interference (ICI), whose effect is intensified when the spectral channel spacing is reduced (for further spectral efficiency increment). In this thesis, we present a study of the ICI effects in Nyquist-WDM systems by means of BER calculation as a function of several system parameters such as: frequency channel spacing, roll-off factor of the digital pulse-shaping filter, laser's linewidth, transmission distance, mark probability of the pseudo-random bit sequence, optical-to-signal noise ratio, among others. Besides, two methods enabling ICI mitigation are proposed: on one hand, a method based on FEC-coded sequence distribution among optical carriers for applications of multiple carriers (superchannels) as a single entity, and on the other hand, a method to perform nonsymmetrical demodulation (NSD) based on the k-means algorithm enabling time-varying distortions mitigation. In contradiction of techniques for ICI mitigation in recent art, these proposals avoid the use of multiple-input multiple-output equalizers or training sequences. Specifically, for NSD approach, information of adjacent channels is not required