The design and implementation of a wideband digital radio receiver

Historically radio has been implemented using largely analogue circuitry. Improvements in mixed signal and digital signal processing technology are rapidly leading towards a largely digital approach, with down-conversion and filtering moving to the digital signal processing domain. Advantages of this technology include increased performance and functionality, as well as reduced cost. Wideband receivers place the heaviest demands on both mixed signal and digital signal processing technology, requiring high spurious free dynamic range (SFDR) and signal processing bandwidths. This dissertation investigates the extent to which current digital technology is able to meet these demands and compete with the proven architectures of analogue receivers. A scalable generalised digital radio receiver capable of operating in the HF and VHF bands was designed, implemented and tested, yielding instantaneous bandwidths in excess of 10 MHz with a spurious-free dynamic range exceeding 80 decibels below carrier (dBc). The results achieved reflect favourably on the digital receiver architecture. While the necessity for minimal analogue circuitry will possibly always exist, digital radio architectures are currently able to compete with analogue counterparts. The digital receiver is simple to manufacture, based on the use of largely commercial off-the-shelf (COTS) components, and exhibits extreme flexibility and high performance when compared with comparably priced analogue receivers

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Implementacija digitalnog generatora obojenog šuma bez množila

Colored noise can be generated by filtering of the white noise. It is a simple task. However, it becomes challenging if high operating speed of the generator is required. The realization of digital filter generally requires one multiplication per coefficient. Therefore, a high operating speed is achieved only with the cost of several generalpurpose multipliers. In this paper, a multiplierless realization of the colored noise generator is proposed. It is based on the filtering of 1-bit random signal by a finite impulse response filter. The design of the generator is described and its implementation is considered. Furthermore, an application is described in which the proposed generator is used in mitigation of undesired effects caused by nonlinearities in an analog to digital converter.Obojeni šum može se generirati filtriranjem bijelog šuma. To je jednostavan postupak. Međutim, on postaje izazovan ako se od generatora traži velika brzina rada. Realizacija digitalnog filtra u pravilu zahtijeva jedno množenje po koeficijentu. Zato se velika brzina rada može postići samo uz cijenu većeg broja množila opće namjene. U ovom radu predložena je realizacija generatora obojenog šuma koja ne sadrži množila. Ona se temelji se na filtraciji 1-bitnog slučajnog signala pomoću filtra s konačnim impulsnim odzivom. Opisano je projektiranje generatora te je razmotrena njegova implementacija. Nadalje, opisana je primjena u kojoj je predloženi generator iskorišten za smanjivanje utjecaja nelinearnosti u analogno digitalnom pretvorniku

Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR

Light Detection and Ranging (LiDAR) is a 3D imaging technique widely used in many applications such as augmented reality, automotive, machine vision, spacecraft navigation and landing. Pulsed-LiDAR is one of the most diffused LiDAR techniques which relies on the measurement of the round-trip travel time of an optical pulse back-scattered from a distant target. Besides the light source and the detector, Time-to-Digital Converters (TDCs) are fundamental components in pulsed-LiDAR systems, since they allow to measure the back-scattered photon arrival times and their performance directly impact on LiDAR system requirements (i.e., range, precision, and measurements rate). In this work, we present a review of recent TDC architectures suitable to be integrated in SPAD-based CMOS arrays and a review of data processing solutions to derive the TOF information. Furthermore, main TDC parameters and processing techniques are described and analyzed considering pulsed-LiDAR requirements

Integrated CMOS Energy Harvesting Converter with Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic Power Generator

This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic (TPV) portable power generator. The design, implemented in 0.35 μm CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 V, and an output voltage of 4 V, we demonstrate a peak conversion efficiency under nominal conditions of over 94% (overall peak efficiency over 95%), at a power level of 300 mW. The control stage uses lossless current sensing together with a custom low-power time-based ADC to minimize control losses. The converter employs a fully integrated digital implementation of a peak power tracking algorithm, and achieves a measured tracking efficiency above 98%. A detailed study of achievable efficiency versus inductor size is also presented, with calculated and measured results.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation