Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

Alternative gate dielectrics and application in nanocrystal memory

Ph.DDOCTOR OF PHILOSOPH

Advanced gate stacks for nano-scale CMOS technology

Ph.DDOCTOR OF PHILOSOPH

Investigation of high-K gate dielectrics for advanced CMOS application

Ph.DDOCTOR OF PHILOSOPH

Hf0.5Zr0.5O2-based ferroelectric devices for digital and analog non-volatile memories

Το διηλεκτρικό υλικό HfO2 έχει χρησιμοποιηθεί εκτενώς τα τελευταία χρόνια και έχει μπει σε βιομηχανική παραγωγή από το 2007 σαν διηλεκτρικό πύλης των τρανζίστορ τεχνολογίας CMOS. Πρόσφατα βρέθηκε ότι το HfO2 είναι σιδηροηλεκτρικό υλικό, όταν κρυσταλλωθεί στη μη κεντροσυμμετρική ορθορομβική δομή. Η κραματοποίησή του με Zr ή ο εμπλουτισμός του με Si, Ge, Al, Gd και άλλες προσμίξεις σταθεροποιεί τη σιδηροηλεκτρική φάση ή τη μετατρέπει σε αντισιδηροηλεκτρική (τετραγωνική δομή). Αυτό ανοίγει νέους δρόμους για πολλές εφαρμογές, συμπεριλαμβανομένων των ενσωματωμένων σιδηροηλεκτρικών μη πτητικών μνημών, αφού το HfO2 και το ZrO2 είναι συμβατά με την τεχνολογία πυριτίου. Στο πλαίσιο της παρούσας διατριβής διερευνήθηκαν οι βέλτιστες συνθήκες σύνθεσης Hf1-xZrxO2 (HZO) για την επίτευξη σιδηροηλεκτρικού υλικού. Δομές πυκνωτών μέταλλο-σιδηροηλεκτρικό-ημιαγωγός (MFS) TiN/HZO/Ge παρασκευάστηκαν με τη μέθοδο της εναπόθεσης με μοριακές δέσμες υποβοηθούμενης από πλάσμα ατομικού οξυγόνου/αζώτου σε θάλαμο υπερυψηλού κενού στο εργαστήριο Μοριακής Επιταξίας και Επιστήμης των Επιφανειών του ΕΚΕΦΕ-Δημόκριτος. Ο δομικός χαρακτηρισμός των πυκνωτών επιβεβαιώνει την επικράτηση της ορθορομβικής/σιδηροηλεκτρικής φάσης του ΗΖΟ και τις καθαρές ΗΖΟ/Ge διεπιφάνειες, οδηγώντας σε καλά σιδηροηλεκτρικά χαρακτηριστικά. Στη συνέχεια, μελετήθηκε η περιοχή απογύμνωσης φορέων στην επιφάνεια του ημιαγωγού Ge, η οποία σχηματίζεται σε χαμηλότερες θερμοκρασίες, και η επίδρασή της στα σιδηροηλεκτρικά χαρακτηριστικά του HZO. Από μετρήσεις της πόλωσης, του ρεύματος μετατόπισης και της χωρητικότητας πυκνωτών σε υποστρώματα γερμανίου p, n και n+ τύπου υπολογίστηκε το πεδίο αποπόλωσης συναρτήσει της θερμοκρασίας. Δύο βασικά φαινόμενα που παίζουν ρόλο στην αξιοπιστία των σιδηροηλεκτρικών διατάξεων είναι η αφύπνιση («wake-up»), δηλαδή η διεύρυνση/βελτίωση του βρόχου P-V εφαρμόζοντας μια σειρά ηλεκτρικών κύκλων, και η αποτύπωση (imprint) της πόλωσης, η οποία είναι η μερική σταθεροποίηση της μίας εκ των δύο πιθανών σιδηροηλεκτρικών καταστάσεων με την πάροδο του χρόνου. Από ηλεκτρικές μετρήσεις της πόλωσης με χρονική και θερμοκρασιακή εξάρτηση, προέκυψαν συμπεράσματα για το μηχανισμό του φαινομένου. Η παραπάνω μελέτη οδήγησε στην παρασκευή σιδηροηλεκτρικών τρανζίστορ επίδρασης πεδίου (FeFETs) με δομή πύλης TiN/HZO σε p-τύπου κανάλι Ge. Αντικαθιστώντας το διηλεκτρικό πύλης των συμβατικών τρανζίστορ με σιδηροηλεκτρικό, παρατηρήθηκε η αναμενόμενη μετατόπιση της χαρακτηριστικής καμπύλης Ids-Vg με την αλλαγή της πόλωσης, εμφανίζοντας ένα παράθυρο μνήμης MW = 0.55 V. Χάρη στη δυνατότητα μερικής στρέψης της πόλωσης στο ΗΖΟ, τα FeFETs εκτός από τις δύο ακραίες καταστάσεις ON και OFF, παρουσιάζουν και ενδιάμεσες καταστάσεις. Αυτό το φαινόμενο τα καθιστά κατάλληλα για εφαρμογή σε αναλογικές μη-πτητικές μνήμες, και χάρη στο μικρό πάχος οξειδίου (15 nm), λειτουργούν με χαμηλή τάση/ισχύ. Τέλος, παρουσιάζονται κάποια αρχικά αποτελέσματα σε πυκνωτές με 5 nm ΗΖΟ σε υποστρώματα ημιαγωγού Nb:SrTiO3 (NSTO) και μεταλλικό TiN ή W ως πάνω ηλεκτρόδιο, τα οποία δείχνουν λειτουργία σύναψης. Η ένταση ρεύματος των πυκνωτών μεταβάλλεται αναλόγως με την κατάσταση πόλωσης του σιδηροηλεκτρικού, κάνοντάς το να λειτουργεί σαν αναλογική μνήμη. Από μετρήσεις ρεύματος σε διάφορες θερμοκρασίες και την ανάλυσή τους, η αγωγιμότητα αποδίδεται σε θερμιονική εκπομπή Schottky και η μεταβολή του ρεύματος στη μεταβολή της αντίστασης στην επιφάνεια του ημιαγωγού, λόγω μεταβολής του φράγματος δυναμικού. Οι διατάξεις παρουσιάζουν πλαστικότητα σύναψης και είναι κατάλληλες για εφαρμογές σε νευρομορφικά δίκτυα.The dielectric material HfO2 has been extensively used in recent years and has entered industrial production since 2007 as a gate dielectric of CMOS technology transistors. HfO2 has recently been found to be ferroelectric when it is crystallized at the non-centrosymmetric orthorhombic phase. Alloying it with Zr or doping it with Si, Ge, Al, Gd and other elements stabilizes the ferroelectric phase or turns it into antiferroelectric (tetragonal phase). This opens new opportunities for many applications, including integrated ferroelectric non-volatile memories, since HfO2 and ZrO2 are compatible with silicon technology. In the present dissertation, the optimal fabrication conditions of Hf1-xZrxO2 (HZO) to achieve a ferroelectric material were investigated. TiN/HZO/Ge metal-ferroelectric-semiconductor (MFS) capacitor structures were prepared by atomic oxygen/nitrogen plasma-assisted molecular beam deposition in an ultrahigh vacuum chamber at the Laboratory of Molecular Epitaxy and Surface Science of NCSR-Demokritos. Physical characterization of the capacitors confirms the predominance of the orthorhombic/ferroelectric phase of HZO and the clean HZO/Ge interfaces, leading to good ferroelectric characteristics. Subsequently, the depletion region in the surface of the Ge semiconductor, formed at lower temperatures, and its effect on the ferroelectric characteristics of HZO were studied. From measurements of polarization, displacement current and capacitor capacitance on p, n and n+ type germanium substrates the depolarization field as a function of temperature was calculated. Two main issues in the reliability of ferroelectric devices are “wake-up”, that is the broadening/improvement of the P-V loop by applying a series of electrical cycles, and polarization imprint, which is the partial stabilization of one of the two possible ferroelectric states over time. From time and temperature depended electrical measurements of the polarization, conclusions about the mechanism of the phenomenon were drawn. The above study led to the fabrication of ferroelectric field-effect transistors (FeFETs) with TiN/HZO gate structure on a p-type Ge channel. By replacing the gate dielectric of conventional transistors with a ferroelectric material, the expected shift of the Ids-Vg characteristic curve with the polarization switching was observed, showing a memory window of MW = 0.55 V. Due to the possibility of partial polarization switching in HZO, FeFETs in addition to the ON and OFF states, also present intermediate states. This phenomenon makes them suitable for application in analog non-volatile memories, and due to the low oxide thickness (15 nm), they operate at low voltage/power. Finally, some first results on capacitors with 5 nm HZO on Nb:SrTiO3 (NSTO) semiconductor substrates and metallic TiN or W as top electrode are presented, which show synaptic performance. The current of the capacitors is modulated by the polarization state in the ferroelectric, making it work as an analog memory. From current measurements at various temperatures and their analysis, the conductivity is attributed to thermionic Schottky emission and the change in current to the change in resistance in the surface of the semiconductor, due to modulation of the potential barrier. The devices show synaptic plasticity and are suitable for applications in neuromorphic networks

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant

Advanced gate stack for sub-0.1 (mu)m CMOS technology

Ph.DDOCTOR OF PHILOSOPH

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book