Internationalisation of Innovation: Why Chip Design Moving to Asia

This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.

NASA space station automation: AI-based technology review

Research and Development projects in automation for the Space Station are discussed. Artificial Intelligence (AI) based automation technologies are planned to enhance crew safety through reduced need for EVA, increase crew productivity through the reduction of routine operations, increase space station autonomy, and augment space station capability through the use of teleoperation and robotics. AI technology will also be developed for the servicing of satellites at the Space Station, system monitoring and diagnosis, space manufacturing, and the assembly of large space structures

NASA SBIR abstracts of 1990 phase 1 projects

The research objectives of the 280 projects placed under contract in the National Aeronautics and Space Administration (NASA) 1990 Small Business Innovation Research (SBIR) Phase 1 program are described. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses in response to NASA's 1990 SBIR Phase 1 Program Solicitation. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 280, in order of its appearance in the body of the report. The document also includes Appendixes to provide additional information about the SBIR program and permit cross-reference in the 1990 Phase 1 projects by company name, location by state, principal investigator, NASA field center responsible for management of each project, and NASA contract number

The propagation of technology management taxonomies for evaluating investments in information systems

To provide managers with a critical insight into the management of new technology, this paper uses a case study research strategy to examine the technology management experiences of a leading UK manufacturing organization during its adoption of a vendor-supplied Manufacturing Resource Planning information system.<br /

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Production Quality for Process Capability with Multiple Characteristics on the Chip Resistor Production

There are many journal papers about process capability indices with multiple characteristics in certain manufacturing assemblies including Cp, Cpk, Cpu, and Cpl. However, all of them assume the data is normal distribution and there is no product level process capability with an example chip resistor. This paper will discuss the affection of sample mean and standard deviations on process capability indices for multiple quality characteristics and its product assembly instead of assuming as normal distributions with the data from simulation. Furthermore, it will present several methodologies to calculate the product process capability with weighted arithmetic mean technique so that we can see how each characteristic effect on the product process

Microprocessor Solder Bump Bridging Defects Screening Strategy In Manufacturing Test Flow

Solder bump bridging (SBB) is a type microprocessor packaging defects in Flip-Chip or C4 interconnection layer. The presence of micro conductive contaminate particle in die-package layer which causes bridging between two or more adjacent solder bump. These contaminate particles are mainly comes from solder bump fraction result from deficient packaging process. Today semiconductor manufacturing test flow is still imperfect to completely screen or detect the SBB defect. As bounce back, the test holes contributes to the defect per million (DPM) of the product. In this research, the test holes of SBB defect in High Volume Manufacturing (HVM) will be defined. Meanwhile, SBB defect characterization will be studied where the electrical behavioural of baby bumps is explained. In the final part of the study, an effective SBB screening test at Burn In is developed to minimizing test holes. From the research finding, un-bridging of SBB occurs at extreme high current of 4.5 A where the baby bump burnt and partial unbridged. This unbridged state are unstable and lacking in term of reliability. However, the SBB un-bridging only impacted on Type B SBB defect where baby bump bridging power bump with ground bump. Lastly, the SBB screening test at Burn In stage is developed as part of this research. In conclusion, the proposed test has the potential in minimizing HVM SBB defect test holes by improving SBB defect fault coverage

Electrostatic Discharge For Sysyem On Chip Applications

Integrated Circuit (IC) component level Electrostatic Discharge (ESD) requisites have stayed constant essentially for past two decades, having said so since the silicon technologies showing rapid advanced and efficacious control methods have prodigiously amended as well as improved. ESD standard JEDEC requirements has been part of success criteria on determine the ESD stress level in semiconductor industry. The standards applied across all product where its specification define for ESD test method, procedure, evaluation and classifying Human Body Model (HBM) a ESD model sensitive on component and ESD sensitivity to charge namely Charged Device Model (CDM). Apparently, the main gaps for this industrial standard missing of defining the withstand ESD stress voltage and recommended step test. Nevertheless, there is room of improvement to recommend guideline for when performing preliminary setup on pin combination for HBM test. In this thesis, will recommend a model change to more authentic but safe ESD stress target levels predicated on actual field data accumulated from 14nm and 22nm differences technology process devices as part of data for the learning on estimation the accuracy of the standards JEDEC JS001 and JS002 requirements on HBM and CDM respectively. Nonetheless, a much effective and time saving way established for data analysis of measurement leakage current increase before and after ESD test using JMP statistics tool on 14nm and 22nm small package devices. Driving to the standardization the new guideline for HBM successfully established. Lastly, the result of this research demonstrates the actual CDM test collected data on 14nm and 22nm more accurate on predicting the withstand voltage compare the peak current methodology

Optimisation Of Milling Parameter And Annealing Condition For Machining Polyetheretherketones (PEEK) Biomaterials Implant

Polyetheretherketones (PEEK) which has been widely used in many applications is now commercialized as implant components because of its biodegradability and non-allergic reactions compared to the metal implants. Generally, implants are fabricated by extrusion and injection molding for a larger scale. However, often for prototype designs or patient specific implant designs, it is not economically viable to manufacture by an injection molding. Under such circumstances, it is common to employ a machining process on the PEEK materials to form the components. However, milling parameters are the factors that have to be considered in the machining process to reduce the defects to the minimum and increase its durability. Apart from milling parameters, annealing also plays important roles in reducing residual stress and improving surface finishes. Thus, this research aims to develop exact milling parameters prior to the annealing process for machining PEEK material in order to enhance the machining performance and productivity. To achieve the objective, both statistical and experimental techniques were employed for the methodology. Response surface methods (RSM) were used to get the mathematical models and ANOVA analysis while milling parameters (feed rate, depth of cut and cutting speed) were used in order to get the machining performance on surface roughness, machining force, dimensional accuracy and material removal rate. Through experiments, the optimised parameters have improved the machining performance and qualities prior to the annaeling. The conclusions provide a theoretical basis for the annealing technique where the increased of the percentage crystalline, it helps improving the properties and the materials structure which leads to improve the machinability of the materials. Milling parameters (feed rate, depth of cut and cutting speed) are important factors in machining process and significantly affect the machining performances. To obtain 0.87μm surface finish, unannealed PEEK with 25.3 percentages crystalline will be using cutting speed 150.8 mm/min, feed rate of 0.035mm/tooth and 2mm depth of cut. PEEK annealed with 200°C increase crystalline to 30.3 percentages using high cutting speed (150.8 mm/min), low feed rate (0.033mm/tooth) and low depth of cut (2mm) can produce 0.4μm surface finish. PEEK annealed with 250°C has 30.9 percentages crystalline and 0.39μm surface finish can be obtained by using high cutting speed (150.8 mm/min), low feed rate (0.034mm/tooth) and low depth of cut (2mm). Therefore, milling machining is recommended to be further used in fabricating PEEK biomedical implants