Nonlinear Analysis and Control of Interleaved Boost Converter Using Real-Time Cycle to Cycle Variable Slope Compensation

Switched-mode power converters are inherently nonlinear and piecewise smooth systems that may exhibit a series of undesirable operations that can greatly reduce the converter's efficiency and lifetime. This paper presents a nonlinear analysis technique to investigate the influence of system parameters on the stability of interleaved boost converters. In this approach, Monodromy matrix that contains all the comprehensive information of converter parameters and control loop can be employed to fully reveal and understand the inherent nonlinear dynamics of interleaved boost converters, including the interaction effect of switching operation. Thereby not only the boundary conditions but also the relationship between stability margin and the parameters given can be intuitively studied by the eigenvalues of this matrix. Furthermore, by employing the knowledge gained from this analysis, a real-Time cycle to cycle variable slope compensation method is proposed to guarantee a satisfactory performance of the converter with an extended range of stable operation. Outcomes show that systems can regain stability by applying the proposed method within a few time periods of switching cycles. The numerical and analytical results validate the theoretical analysis, and experimental results verify the effectiveness of the proposed approach

Simulations of III-V NWFET Double-Balanced Gilbert Cells with an Improved Noise Model

III-V nanowire transistors might provide a mean for extending Moore’s law, by overcoming the scaling limitations ultimately facing planar silicon CMOS. These high frequency capable transistors with cut-off frequencies in the terahertz regime are suitable for radio communication. In this project an active double-balanced gilbert cell mixer consisting of nanowire field-effect transistors (NWFETs) was simulated in Cadence Virtuoso using a compact transistor model. The transistor model was extended to take flicker and thermal noise into account, in order to more accurately compare the mixers against state-of-the-art silicon CMOS implementations. The final mixer for 60 GHz showed much greater linearity (0.4 dBm 1 dB compression and 8.5 dBm IIP 3) than previously reported silicon CMOS counterparts. It exhibited a conversion gain of 3.47 dB, a N F DSB of 14.6 dB and a DC power consumption of 8.7 mW.Based on these findings the design requirements for suitable low noise amplifier was discussed

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition

Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient ANOVA-based stochastic circuit/MEMS simulator to extract efficiently the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is simulated efficiently by our simulator at the cost of only 10 minutes in MATLAB on a regular personal computer.Comment: 14 pages (IEEE double column), 11 figure, accepted by IEEE Trans CAD of Integrated Circuits and System

Sub-Nyquist Sampling: Bridging Theory and Practice

Sampling theory encompasses all aspects related to the conversion of continuous-time signals to discrete streams of numbers. The famous Shannon-Nyquist theorem has become a landmark in the development of digital signal processing. In modern applications, an increasingly number of functions is being pushed forward to sophisticated software algorithms, leaving only those delicate finely-tuned tasks for the circuit level. In this paper, we review sampling strategies which target reduction of the ADC rate below Nyquist. Our survey covers classic works from the early 50's of the previous century through recent publications from the past several years. The prime focus is bridging theory and practice, that is to pinpoint the potential of sub-Nyquist strategies to emerge from the math to the hardware. In that spirit, we integrate contemporary theoretical viewpoints, which study signal modeling in a union of subspaces, together with a taste of practical aspects, namely how the avant-garde modalities boil down to concrete signal processing systems. Our hope is that this presentation style will attract the interest of both researchers and engineers in the hope of promoting the sub-Nyquist premise into practical applications, and encouraging further research into this exciting new frontier.Comment: 48 pages, 18 figures, to appear in IEEE Signal Processing Magazin