One-Dimensional Lazy Quantum walk in Ternary System

Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here we present one dimensional three-state quantum walk(lazy quantum walk) and show its equivalence for circuit realization in ternary quantum logic for the first of its kind. Using an appropriate logical mapping of the position space on which a walker evolves onto the multi-qutrit states, we present efficient quantum circuits considering the nearest neighbour position space for the implementation of lazy quantum walks in one-dimensional position space in ternary quantum system. We also address scalability in terms of $n$-qutrit ternary system with example circuits for a three qutrit state space.Comment: 13 pages, 12 figures, and 10 table

A Lightweight Implementation of NTRUEncrypt for 8-bit AVR Microcontrollers

Introduced in 1996, NTRUEncrypt is not only one of the earliest but also one of the most scrutinized lattice-based cryptosystems and a serious contender in NIST’s ongoing Post-Quantum Cryptography (PQC) standardization project. An important criterion for the assessment of candidates is their computational cost in various hardware and software environments. This paper contributes to the evaluation of NTRUEncrypt on the ATmega class of AVR microcontrollers, which belongs to the most popular 8-bit platforms in the embedded domain. More concretely, we present AvrNtru, a carefully-optimized implementation of NTRUEncrypt that we developed from scratch with the goal of achieving high performance and resistance to timing attacks. AvrNtru complies with version 3.3 of the EESS#1 specification and supports recent product-form parameter sets like ees443ep1, ees587ep1, and ees743ep1. A full encryption operation (including mask generation and blinding- polynomial generation) using the ees443ep1 parameters takes 834,272 clock cycles on an ATmega1281 microcontroller; the decryption is slightly more costly and has an execution time of 1,061,683 cycles. When choosing the ees743ep1 parameters to achieve a 256-bit security level, 1,539,829 clock cycles are cost for encryption and 2,103,228 clock cycles for decryption. We achieved these results thanks to a novel hybrid technique for multiplication in truncated polynomial rings where one of the operands is a sparse ternary polynomial in product form. Our hybrid technique is inspired by Gura et al’s hybrid method for multiple-precision integer multiplication (CHES 2004) and takes advantage of the large register file of the AVR architecture to minimize the number of load instructions. A constant-time multiplication in the ring specified by the ees443ep1 parameters requires only 210,827 cycles, which sets a new speed record for the arithmetic component of a lattice-based cryptosystem on an 8-bit microcontroller

Constructing all qutrit controlled Clifford+T gates in Clifford+T

For a number of useful quantum circuits, qudit constructions have been found which reduce resource requirements compared to the best known or best possible qubit construction. However, many of the necessary qutrit gates in these constructions have never been explicitly and efficiently constructed in a fault-tolerant manner. We show how to exactly and unitarily construct any qutrit multiple-controlled Clifford+T unitary using just Clifford+T gates and without using ancillae. The T-count to do so is polynomial in the number of controls $k$, scaling as $O(k^{3.585})$. With our results we can construct ancilla-free Clifford+T implementations of multiple-controlled T gates as well as all versions of the qutrit multiple-controlled Toffoli, while the analogous results for qubits are impossible. As an application of our results, we provide a procedure to implement any ternary classical reversible function on $n$ trits as an ancilla-free qutrit unitary using $O(3^n n^{3.585})$ T gates.Comment: 14 page

Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed nn-qudit Toffoli Gate

As the development of Quantum computers becomes reality, the implementation of quantum algorithms is accelerating in a great pace. Grover's algorithm in a binary quantum system is one such quantum algorithm which solves search problems with numeric speed-ups than the conventional classical computers. Further, Grover's algorithm is extended to a $d$-ary quantum system for utilizing the advantage of larger state space. In qudit or $d$-ary quantum system n-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this paper, a generalized $n$-qudit Toffoli gate has been realized using qudits to attain a logarithmic depth decomposition without ancilla qudit. Further, the circuit for Grover's algorithm has been designed for any d-ary quantum system, where d >= 2, with the proposed $n$-qudit Toffoli gate so as to get optimized depth as compared to state-of-the-art approaches. This technique for decomposing an n-qudit Toffoli gate requires access to higher energy levels, making the design susceptible to leakage error. Therefore, the performance of this decomposition for the unitary and erasure models of leakage noise has been studied as well

Photonic integrated reconfigurable linear processors as neural network accelerators

Reconfigurable linear optical processors can be used to perform linear transformations and are instrumental in effectively computing matrix–vector multiplications required in each neural network layer. In this paper, we characterize and compare two thermally tuned photonic integrated processors realized in silicon-on-insulator and silicon nitride platforms suited for extracting feature maps in convolutional neural networks. The reduction in bit resolution when crossing the processor is mainly due to optical losses, in the range 2.3–3.3 for the silicon-on-insulator chip and in the range 1.3–2.4 for the silicon nitride chip. However, the lower extinction ratio of Mach–Zehnder elements in the latter platform limits their expressivity (i.e., the capacity to implement any transformation) to 75%, compared to 97% of the former. Finally, the silicon-on-insulator processor outperforms the silicon nitride one in terms of footprint and energy efficiency

Photonic Integrated Reconfigurable Linear Processors as Neural Network Accelerators

Reconfigurable linear optical processors can be used to perform linear transformations and are instrumental in effectively computing matrix-vector multiplications required in each neural network layer. In this paper, we characterize and compare two thermally tuned photonic integrated processors realized in silicon-on-insulator and silicon nitride platforms suited for extracting feature maps in convolutional neural networks. The reduction in bit resolution when crossing the processor is mainly due to optical losses, in the range 2.3-3.3 for the silicon-on-insulator chip and in the range 1.3-2.4 for the silicon nitride chip. However, the lower extinction ratio of Mach-Zehnder elements in the latter platform limits their expressivity (i.e., the capacity to implement any transformation) to 75%, compared to 97% of the former. Finally, the silicon-on-insulator processor outperforms the silicon nitride one in terms of footprint and energy efficiency