대역 외 방해신호에 내성을 가지는 광대역 수신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 남상욱.In this thesis, a study of wideband receivers as one of the practical SDR receiver implementations is presented. The out-of-band interference signal (or blocker), which is the biggest problem of the wideband receiver is investigated, and have studied how to effectively remove it. As a result of reviewing previous studies, we have developed a wideband receiver based on the current-mode receiver structure and attempted to eliminate the blocker. The contents of the step-by-step research are as follows. First, attention was paid to the linearity of a low-noise transconductance amplifier (LNTA), which is the base block of current-mode receivers. In current-mode receivers, the LNTA should have a high transconductance (Gm) value to achieve a low noise figure, but a high Gm value results in low linearity. To solve this trade-off, we proposed a linearization method of transconductors. The proposed technique eliminates the third-order intermodulation distortion (IMD3) in a feed-forward manner using two paths. A transconductor having a transconductance of 2Gm is disposed in the main path, and an amplifier having a gain of ∛2 and a Gm-sized transconductor are located in the auxiliary path. This structure allows for some fundamental signal loss but cancel the IMD3 component at the output. As a result, the entire transconductor circuit can have high linearity due to the removed IMD3 component. We have designed a reconfigurable high-pass filter using a linearized transconductor and have demonstrated its performance. The fabricated circuit achieved a high input-referred third-order intercept point(IIP3) performance of 19.4 dBm. Then, a further improved linearized transconductor is designed. Since the linearized transconductors have a high noise figure due to the additional circuitry used for linearization, we have proposed a more suitable form for application to LNTA through noise figure analysis. The improved LNTA is designed to operate in low noise mode when there is no blocker, and can be switched to operate in high linearity mode when the blocker exists. We also applied noise cancelling techniques to the receiver to improve the noise figure performance of the wideband receiver circuit. A feedback path has been added to the current-mode receiver structure consisting of the LNTA, the mixer and the baseband transimpedance amplifier (TIA), and the noise signal can be detected using this path. This feedback path also maintains the input matching of the receiver to 50 Ω in a wide bandwidth. By adding an auxiliary path to the receiver, the in-band signal is amplified and the detected noise is removed from the baseband. The completed circuit exhibited wideband performance from 0.025 GHz to 2 GHz and IIP3 performance of -6.9 dBm in the high linearity mode. Finally, we designed a double noise-cancelling wideband receiver circuit by improving the performance of a wideband receiver with high immunity to blocker signals. In previous receivers, the LNTA was operated in two modes depending on the situation. In the improved receiver, the Gm ratio of the linearized LNTA was changed and the RF noise-cancelling technique was applied. The input matching and noise cancelling scheme introduced in the previous circuit was also applied and a wideband receiver circuit was designed to perform double noise-cancelling. As a result, the linearization and noise-cancellation of LNTA could be achieved at the same time, and the completed receiver circuit showed high IIP3 performance of 5 dBm with minimum noise figure of 1.4 dB. In conclusion, this thesis proposed a linearization technique for transconductor circuit and designed a wideband receiver based on current-mode receiver. The designed receiver circuit experimentally verified that it has low noise figure performance and high IIP3 performance and is tolerant to out-of-band blocker signals.Chapter 1. Introduction 1 1.1. Motivation of Wideband Receiver Architecture 2 1.2. Challenges in Designing Wideband Receiver 7 1.3. Prior Researches 13 1.3.1. N-Path Filter 14 1.3.2. Feed-Forward Blocker Filtering 16 1.3.3. Current-Mode Receiver 18 1.4. Research Objectives and Thesis Organization 22 Chapter 2. Transconductor Linearization Technique and Design of Tunable High-pass Filter 24 2.1. Transconductor Linearization Technique 27 2.2. Design of Tunable High-pass Filter 36 2.3. Measurement Results 41 2.4. Conclusions 46 Chapter 3. Wideband Noise-Cancelling Receiver Front-End Using Linearized Transconductor 47 3.1. Low-Noise Transconductance Amplifier Based on Linearized Transconductor 49 3.2. Wideband Noise-Cancelling Receiver Architecture 58 3.3. Measurement Results 64 3.4. Conclusions 70 Chapter 4. Blocker-Tolerant Wideband Double Noise-Cancelling Receiver Front-End 71 4.1. Linearized Noise-Cancelling Low-Noise Transconductance Amplifier 73 4.2. Wideband Double Noise-Cancelling Receiver Front-End 83 4.3. Measurement Results 90 4.4. Conclusions 97 Chapter 5. Conclusions 98 Bibliography 102 Abstract in Korean 112Docto

Frequency Translation loops for RF filtering-Theory and Design

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particular, dealing with interfer- ence scenarios is crucial since they directly translate to higher linearity requirements in a receiver. With CMOS driving the consumer electronics market due to low cost and high level of integration demands, the continued increase in speed, mainly intended for digital applications, oers new possibilities for RF design to improve the linearity of front-end receivers. Furthermore, the readily available switches in CMOS have proven to be a viable alternative to traditional active mixers for frequency translation due to their high linearity, low flicker noise, and, most recently recognized, their impedance transformation properties. In this thesis, frequency translation feedback loops employing passive mixers are explored as a means to relax the linearity requirements in a front-end receiver by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture employing such loop addresses some of the most common prob- lems of integrated RF lters, while maintaining their inherent tunability. Through a simplied and intuitive analysis, the operation of the receiver is first examined and the design parameters aecting the lter characteristics, such as band- width and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-o between noise, linearity and harmonic radiation. Next, a detailed analysis of frequency translation loops using passive mixers is developed. Only highly simplied analysis of such loops is commonly available in literature. The analysis is based on an iterative procedure to address the complexity introduced by the presence of LO harmonics in the loop and the lack of reverse isolation in the mixers, and results in highly accurate expressions for the harmonic and noise transfer functions of the system. Compared to the alternative of applying general LPTV theory, the procedure developed oers more intuition into the operation of the system and only requires the knowledge of basic Fourier analysis. The solution is shown to be capable of predicting trade-os arising due to harmonic mixing and loop stability requirements, and is therefore useful for both system design and optimization. Finally, as a proof of concept, a chip prototype is designed in a standard 65nm CMOS process. The design occupies +12dBm. As such, the work presented in this thesis aims to provide a highly-integrated means for programmable RF channel selection in wideband receivers. The topic oers several possibilities for further research, either in terms of extending the viability of the system, for example by providing higher order ltering, or by improving performance, such as noise

Low Power Filtering Techniques for Wideband and Wireless Applications

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Polyphase filter with parametric tuning

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 201

Techniques de conception de circuits analogiques intégrés à haute performance en CMOS

Amplificateurs opérationnels à réaction en courant et circuits de transconductance à hautes fréquences en technologie CMOS -- Amplificateurs opérationnels à réaction en courant -- Circuits de transconductance CMOS (VCT) -- Amplificateur opérationnel à réaction en courant, de gain élevé et de tension de décalage réduite -- An offset compensated and high gain CMOS current-feedback op.-amp. -- Technique de compensation pour réduire la tension de décalage et l'erreur de gain des amplificateurs opérationnels à réaction en courant en technologie CMOS : Conception et mesures -- Compensation technique to reduce offset and gain error of CMOS CFOA : design and subsequent measurements -- Circuit de transconductance à hautes performances en technologie CMOS pour les applications mixtes analogiques et numériques -- High performance CMOS transconductor for mixed-signal analog-digital applications -- Nouvelle architecture d'un CFOA en CMOS (partie A) -- Nouvelle architecture d'un VCT en CMOS (partie B)

Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization

This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm

Linearity vs. Power Consumption of CMOS LNAs in LTE Systems

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) system. Using proposed figure of merit to compare 35 state-of-the-art LNA circuits published in recent years, the paper shows a proportional but relatively weak dependence between amplifier performance (that is combined linearity, noise figure and gain) with power consumption. As a result, the predicted increase of LNA performance, necessary to satisfy stringent linearity specifications of LTE standard, may require a significant increase in power, a critical budget planning aspect for both handheld devices and base stations operating in small cells

Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver