Quasi-orthogonal space-frequency coding in non-coherent cooperative broadband networks

© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.So far, complex valued orthogonal codes have been used differentially in cooperative broadband networks. These codes however achieve less than unitary code rate when utilized in cooperative networks with more than two relays. Therefore, the main challenge is how to construct unitary rate codes for non-coherent cooperative broadband networks with more than two relays while exploiting the achievable spatial and frequency diversity. In this paper, we extend full rate quasi-orthogonal codes to differential cooperative broadband networks where channel information is unavailable. From this, we propose a generalized differential distributed quasi-orthogonal space-frequency coding (DQSFC) protocol for cooperative broadband networks. Our proposed scheme is able to achieve full rate, and full spatial and frequency diversity in cooperative networks with any number of relays. Through pairwise error probability analysis we show that the diversity gain of our scheme can be improved by appropriate code construction and sub-carrier allocation. Based on this, we derive sufficient conditions for the proposed code structure at the source node and relay nodes to achieve full spatial and frequency diversity.Peer reviewe

Software trace cache

We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimizations. We target not only an improvement in the instruction cache hit rate, but also an increase in the effective fetch width of the fetch engine. The STC algorithm organizes basic blocks into chains trying to make sequentially executed basic blocks reside in consecutive memory positions, then maps the basic block chains in memory to minimize conflict misses in the important sections of the program. We evaluate and analyze in detail the impact of the STC, and code layout optimizations in general, on the three main aspects of fetch performance; the instruction cache hit rate, the effective fetch width, and the branch prediction accuracy. Our results show that layout optimized, codes have some special characteristics that make them more amenable for high-performance instruction fetch. They have a very high rate of not-taken branches and execute long chains of sequential instructions; also, they make very effective use of instruction cache lines, mapping only useful instructions which will execute close in time, increasing both spatial and temporal locality.Peer ReviewedPostprint (published version