RTS noise impact in CMOS image sensors readout circuit

CMOS image sensors are nowadays widely used in imaging applications even for high end applications. This is really possible thanks to a reduction of noise obtained, among others, by Correlated Double Sampling (CDS) readout. Random Telegraph Signal (RTS) noise has thus become an issue for low light level applications especially in the context of downscaling transistor dimension. This paper describes the analysis of in-pixel source follower transistor RTS noise filtering by CDS circuit. The measurement of a non Gaussian distribution with a positive skew of image sensor output noise is analysed and dimension (W and L) impact of the in-pixel source follower is analysed

Low-frequency noise impact on CMOS image sensors

CMOS image sensors are nowadays extensively used in imaging applications even for high-end applications. This is really possible thanks to a reduction of noise obtained, among others, by Correlated Double Sampling (CDS) readout. Random Telegraph Signal (RTS) noise has thus become an issue for low light level applications especially in the context of downscaling transistor size. This paper describes the analysis of in-pixel source follower transistor RTS noise filtering by CDS circuit. The measurement of a non Gaussian distribution with a positive skew of image sensor output noise is analysed. Impact of dimensions (W and L) of the in-pixel source follower is demonstrated. Circuit to circuit pixel output noise dispersion on 12 circuits coming from 3 different wafers is also analysed and weak dispersion is seen

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Dynamic range optimisation of CMOS image sensors dedicated to space applications

Nowadays, CMOS image sensors are widely considered for space applications. Their performances have been significantly enhanced with the use of CIS (CMOS Image Sensor) processes in term of dark current, quantum efficiency and conversion gain. Dynamic Range (DR) remains an important parameter for a lot of applications. Most of the dynamic range limitation of CMOS image sensors comes from the pixel. During work performed in collaboration with EADS Astrium, SUPAERO/CIMI laboratory has studied different ways to improve dynamic range and test structures have been developed to perform analysis and characterisation. A first way to improve dynamic range will be described, consisting in improving the voltage swing at the pixel output. Test vehicles and process modifications made to improve voltage swing will be depicted. We have demonstrated a voltage swing improvement more than 30%. A second way to improve dynamic range is to reduce readout noise A new readout architecture has been developed to perform a correlated double sampling readout. Strong readout noise reduction will be demonstrated by measurements performed on our test vehicle. A third way to improve dynamic range is to control conversion gain value. Indeed, in 3 TMOS pixel structure, dynamic range is related to conversion gain through reset noise which is dependant of photodiode capacitance. Decrease and increase of conversion gain have been performed with different design techniques. A good control of the conversion gain will be demonstrated with variation in the range of 0.05 to 3 of initial conversion gain

Energy Efficient Engine (E3) controls and accessories detail design report

An Energy Efficient Engine program has been established by NASA to develop technology for improving the energy efficiency of future commercial transport aircraft engines. As part of this program, a new turbofan engine was designed. This report describes the fuel and control system for this engine. The system design is based on many of the proven concepts and component designs used on the General Electric CF6 family of engines. One significant difference is the incorporation of digital electronic computation in place of the hydromechanical computation currently used

Analysis and Optimization of Noise Response for Low-Noise CMOS Image Sensors

CMOS image sensors are nowadays widely used in imaging applications and particularly in low light flux applications. This is really possible thanks to a reduction of noise obtained, among others, by the use of pinned photodiode associated with a Correlated Double Sampling readout. It reveals new noise sources which become the major contributors. This paper presents noise measurements on low-noise CMOS image sensor. Image sensor noise is analyzed and optimization is done in order to reach an input referred noise of 1 electron rms by column gain amplifier insertion and dark current noise optimization. Pixel array noise histograms are analyzed to determine noise impact of dark current and column gain amplifier insertion. Transfer noise impact, due to the use of pinned photodiode (4T photodiode), is also measured and analyzed by a specific readout sequence

Quantum algorithm for simulating the dynamics of an open quantum system

In the study of open quantum systems, one typically obtains the decoherence dynamics by solving a master equation. The master equation is derived using knowledge of some basic properties of the system, the environment and their interaction: one basically needs to know the operators through which the system couples to the environment and the spectral density of the environment. For a large system, it could become prohibitively difficult to even write down the appropriate master equation, let alone solve it on a classical computer. In this paper, we present a quantum algorithm for simulating the dynamics of an open quantum system. On a quantum computer, the environment can be simulated using ancilla qubits with properly chosen single-qubit frequencies and with properly designed coupling to the system qubits. The parameters used in the simulation are easily derived from the parameters of the system+environment Hamiltonian. The algorithm is designed to simulate Markovian dynamics, but it can also be used to simulate non-Markovian dynamics provided that this dynamics can be obtained by embedding the system of interest into a larger system that obeys Markovian dynamics. We estimate the resource requirements for the algorithm. In particular, we show that for sufficiently slow decoherence a single ancilla qubit could be sufficient to represent the entire environment, in principle.Comment: 5 figures, two table

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture

Neural Network (NN) accelerators with emerging ReRAM (resistive random access memory) technologies have been investigated as one of the promising solutions to address the \textit{memory wall} challenge, due to the unique capability of \textit{processing-in-memory} within ReRAM-crossbar-based processing elements (PEs). However, the high efficiency and high density advantages of ReRAM have not been fully utilized due to the huge communication demands among PEs and the overhead of peripheral circuits. In this paper, we propose a full system stack solution, composed of a reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and its software system including neural synthesizer, temporal-to-spatial mapper, and placement & routing. We highly leverage the software system to make the hardware design compact and efficient. To satisfy the high-performance communication demand, we optimize it with a reconfigurable routing architecture and the placement & routing tool. To improve the computational density, we greatly simplify the PE circuit with the spiking schema and then adopt neural synthesizer to enable the high density computation-resources to support different kinds of NN operations. In addition, we provide spiking memory blocks (SMBs) and configurable logic blocks (CLBs) in hardware and leverage the temporal-to-spatial mapper to utilize them to balance the storage and computation requirements of NN. Owing to the end-to-end software system, we can efficiently deploy existing deep neural networks to FPSA. Evaluations show that, compared to one of state-of-the-art ReRAM-based NN accelerators, PRIME, the computational density of FPSA improves by 31x; for representative NNs, its inference performance can achieve up to 1000x speedup.Comment: Accepted by ASPLOS 201