Automated Circuit Approximation Method Driven by Data Distribution

We propose an application-tailored data-driven fully automated method for functional approximation of combinational circuits. We demonstrate how an application-level error metric such as the classification accuracy can be translated to a component-level error metric needed for an efficient and fast search in the space of approximate low-level components that are used in the application. This is possible by employing a weighted mean error distance (WMED) metric for steering the circuit approximation process which is conducted by means of genetic programming. WMED introduces a set of weights (calculated from the data distribution measured on a selected signal in a given application) determining the importance of each input vector for the approximation process. The method is evaluated using synthetic benchmarks and application-specific approximate MAC (multiply-and-accumulate) units that are designed to provide the best trade-offs between the classification accuracy and power consumption of two image classifiers based on neural networks.Comment: Accepted for publication at Design, Automation and Test in Europe (DATE 2019). Florence, Ital

Fusion of imprecise qualitative information

In this paper, we present a new 2-tuple linguistic representation model, i.e. Distribution Function Model (DFM), for combining imprecise qualitative information using fusion rules drawn from Dezert-Smarandache Theory (DSmT) framework. Such new approach allows to preserve the precision and efficiency of the combination of linguistic information in the case of either equidistant or unbalanced label model. Some basic operators on imprecise 2-tuple labels are presented together with their extensions for imprecise 2-tuple labels. We also give simple examples to show how precise and imprecise qualitative information can be combined for reasoning under uncertainty. It is concluded that DSmT can deal efficiently with both precise and imprecise quantitative and qualitative beliefs, which extends the scope of this theory

Privacy Leakages in Approximate Adders

Approximate computing has recently emerged as a promising method to meet the low power requirements of digital designs. The erroneous outputs produced in approximate computing can be partially a function of each chip's process variation. We show that, in such schemes, the erroneous outputs produced on each chip instance can reveal the identity of the chip that performed the computation, possibly jeopardizing user privacy. In this work, we perform simulation experiments on 32-bit Ripple Carry Adders, Carry Lookahead Adders, and Han-Carlson Adders running at over-scaled operating points. Our results show that identification is possible, we contrast the identifiability of each type of adder, and we quantify how success of identification varies with the extent of over-scaling and noise. Our results are the first to show that approximate digital computations may compromise privacy. Designers of future approximate computing systems should be aware of the possible privacy leakages and decide whether mitigation is warranted in their application.Comment: 2017 IEEE International Symposium on Circuits and Systems (ISCAS

MSB-First Interval-Bounded Variable-Precision RealTime Arithmetic Unit

This paper presents a paradigm of real-time processing on the lowest level of computing systems: the arithmetic unit. The arithmetic unit based on this principle containing addition, subtraction, multiplication and division operations is  described.  The  development  of  the  computation  model  is  based  on  the  Soft Computing and the Imprecise Computation paradigms, combined with the MSBFirst  and  the  Interval  Arithmetic  techniques.  Those  paradigms  and  techniques give  the  arithmetic  unit  design  the  ability  to  compute  with  precisions  as  a function  of time available or accuracy needed. The predictability of processing time and result's accuracy are obtained by means of processing granularity of k bits and by  using look-up tables. We present an evaluation of  the operation in time  delay  and  computation  accuracy  that  shows  significant  performance improvement over conventional arithmetic unit architecture, that is,  the ability to produce  intermediate-result  during  execution  time,  to  give  certainty  in computation  accuracy  even  before  the  process  finish  time  by  providing  two intermediate-results,  which  act  as  the  lower  and  upper  bound  of  the  real  and complete computation result, and finally, gain high computation accuracy from the early time of the execution process

A course on digital electronics based on solving design-oriented exercises by means of a PBL strategy

Recently, new syllabuses are being implemented accordingly to the European Higher Education Area (EHEA) in Spain. This paper describes the methodology and assessment strategy applied in the subject ‘‘Digital Circuits and Systems’’ (CSD) in the third semester course in the Telecommunications Engineering degree at the Castelldefels School of Telecommunications and Aerospace Engineering (EETAC) of the Universitat Polite`cnica de Catalunya (UPC). The course’s main learning objective is that students be able to analyse and design simple combinational and sequential circuits by means of hardware description languages for programmable devices and program applications using microcontrollers and C language. Small groups of two or three students work in cooperation using PBL techniques to solve design-oriented assignments, while instructors act more as mediators than lecturers in order to facilitate project development and knowledge acquisition. The experience we describe corresponds to the spring term of 2011, a period in which this methodology was applied to 46 students. This work compares statistically the influence of the students’ background on their academic performance in our subject. A significant correlation has been detected between test marks and the final grade, based on continuous assessment. Students’ opinions have been obtained by means of a survey at the end of the course. Although the high workload and involvement, because this methodology requires constancy and commitment from the students, most of them have positive opinions on the development of the subject, due to the fact that they realise that they have put into practice several competences or cross-curricular skills, while acquiring the course content, and furthermore, most of them have passed the course, even with higher grades than the ones from other subjects in the same semester.Peer ReviewedPostprint (published version

Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization

Designing digital circuits well is notoriously difficult. This difficulty stems in part from the very many degrees of freedom inherent in circuit design, typically coupled with the need to satisfy various constraints. In this thesis, we demonstrate how formulations of satisfiability problems can be used automatically to complete a design, or to find a specific design architecture that satisfies certain constraints; how these can be used to create, debug, and optimize designs; and introduce a domain-specific language particularly well-suited for satisfiability-assisted design, debug, and optimization. In the first application, we show how explicit uncertainties called âholesâ can both be natural to use and conducive to the creation of formal satisfiability problems useful for designing circuits. We further develop a Scala-hosted Domain Specific Language (DSL) with appropriate syntactic sugar to make design with holes easy and effective. We then show how, utilizing the same kind of satisfiability formulation, we can automatically instrument a given buggy design to replace suspicious syntax fragments with potentially-correct alternatives. The satisfiability solver then determines if there is any possible set of alternative fragments which fix the bug. We also demonstrate that this approach is reasonably scalable, in part because there is less need for a fully-precise specification in the formulation of the satisfiability problem. We then advance beyond mere hole-filling and show how a tight integration of design elaboration with satisfiability solvers allows totally new approaches. To point, we use this tight integration to create the first known methods to optimize Gate-Level Information Flow Track- ing (GLIFT) model circuits and to make principled trade-offs in their precision. Finally, integrating all the previous work, we propose a more powerful DSL specifically designed to address the shortcomings of the first âhole-fillingâ language. This language, which we call Nasadiya, affords more general integrations of satisfiability into circuit design and optimization, and provides built-in modeling functionality useful for optimizing extra-functional properties like critical path delay and circuit area. We demonstrate the utility of these features by implementing an automatic power optimizer for a popular type of parallel prefix adders