Hardware for Dynamic Quantum Computing

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fedback or fedforward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow on a fraction superconducting qubit coherence times. Both readout and control platforms make extensive use of FPGAs to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development

Implementation of Energy Efficient Single Flux Quantum (eSFQ) Digital Circuits with sub-aJ/bit Operation

We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.Comment: 28 Page

Paving the Way to Simpler: Experiencing from Maximizing Enrollment States in Streamlining Eligibility and Enrollment

Since 2009, the eight states (Alabama, Illinois, Louisiana, Massachusetts, New York, Utah, Virginia, and Wisconsin) participating in the Robert Wood Johnson Foundation's Maximizing Enrollment program have worked to streamline and simplify enrollment systems, policies, and processes for children and those eligible for health coverage in 2014. The participating states aimed to reduce enrollment barriers for consumers and administrative burdens in processing applications and renewals for staff by making improvements and simplifications at every step of the enrollment process. Although the states began their work before the enactment of the Affordable Care Act (ACA), their efforts positioned them well for implementation in 2014, and offer experiences and lessons that other states may find useful in their efforts to improve efficiency, lower costs, and promote responsible stewardship of limited public resources

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report

This is the second of a planned collection of four yearly volumes describing the deployment of a heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications. This volume covers several topics, among which: 1- a system for awareness of faults and critical events (named LO|FA|MO) on experimental heterogeneous many-core hardware platforms; 2- the integration and test of the experimental hardware heterogeneous many-core platform QUoNG, based on the APEnet+ custom interconnect; 3- the design of a Software-Programmable Distributed Network Processor architecture (DNP) using ASIP technology; 4- the initial stages of design of a new DNP generation onto a 28nm FPGA. These developments were performed in the framework of the EURETILE European Project under the Grant Agreement no. 247846.Comment: 119 page

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente

BioMeT and algorithm challenges: A proposed digital standardized evaluation framework

Technology is advancing at an extraordinary rate. Continuous flows of novel data are being generated with the potential to revolutionize how we better identify, treat, manage, and prevent disease across therapeutic areas. However, lack of security of confidence in digital health technologies is hampering adoption, particularly for biometric monitoring technologies (BioMeTs) where frontline healthcare professionals are struggling to determine which BioMeTs are fit-for-purpose and in which context. Here, we discuss the challenges to adoption and offer pragmatic guidance regarding BioMeTs, cumulating in a proposed framework to advance their development and deployment in healthcare, health research, and health promotion. Furthermore, the framework proposes a process to establish an audit trail of BioMeTs (hardware and algorithms), to instill trust amongst multidisciplinary users

Towards Programmable Network Dynamics: A Chemistry-Inspired Abstraction for Hardware Design

Chemical algorithms are statistical algorithms described and represented as chemical reaction networks. They are particularly attractive for traffic shaping and general control of network dynamics; they are analytically tractable, they reinforce a strict state-to-dynamics relationship, they have configurable stability properties, and they are directly implemented in state-space using a high-level (graphical) representation. In this paper, we present a direct implementation of chemical algorithms on FPGA hardware. Besides substantially improving performance, we have achieved hardware-level programmability and re-configurability of these algorithms at runtime (not interrupting servicing) and in realtime (with sub-second latency). This opens an interesting perspective for expanding the currently limited scope of software defined networking and network virtualisation solutions, to include programmable control of network dynamics.Comment: 14 pages, non accepted version submitted to IEEE/ACM Transactions on Networking on May 2015 (after first submission on May 2014

Making FPGAs Accessible to Scientists and Engineers as Domain Expert Software Programmers with LabVIEW

In this paper we present a graphical programming framework, LabVIEW, and associated language and libraries, as well as programming techniques and patterns that we have found useful in making FPGAs accessible to scientists and engineers as domain expert software programmers.Comment: Presented at First International Workshop on FPGAs for Software Programmers (FSP 2014) (arXiv:1408.4423

Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications

Real time data acquisition systems in nuclear science often rely on high-speed logic designs to reach the fast data rate requirements. They are mostly coded in a hardware description language (HDL). However, in recent years, high level synthesis (HLS) compilers have appeared, with the notable advantage that they rely on the widespread C/C++ syntax. This paper's aim is to outline differences between HDL and C/C++ HLS based designs for two real-time data acquisition modules used in nuclear science. The first module is a real-time crystal identification module, and the second is a compact event timestamp sorting module. This evaluation was done by an experienced VHDL programmer with no prior HLS training. For the crystal identification module, both HDL and HLS versions have the same event processing interval, and the HLS implementation consumes twice as many lookup tables and flip flops as the HDL version. On the other hand, the HLS version took half the time to write and debug. For the sorter module, the HLS version requires about 3 to 4 times more logic resources, with a slightly longer processing interval. It was also completed in half the time compared to the original HDL code. While different compiler directives can still be explored to improve source code clarity, resource usage and timing closure in these designs, this trial shows that HLS is a compelling alternative to custom HDL implementations for real time systems in nuclear and plasma science.Comment: IEEE NPSS Real Time Conference Record, 201