EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards

Evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. The architecture of a complete Fault Injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. To address this issue, the paper describes a software-implemented Fault Injection approach based on the Trace Exception Mode available in most microprocessors. The authors describe EXFI, a prototypical system implementing the approach, and provide data about some sample benchmark applications. The main advantages of EXFI are the low cost, the good portability, and the high efficienc

The design and implementation of an I/O controller for the 386EX evaluation board

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 58-60).by Marcus-Alan Gilbert.M.Eng

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated

Design and Implementation of Cerebral Model Neural Network based Controller using VxWorksRTOS ported toMPC8260

Abstract: With the development of embedded Real Time Operating System (RTOS), dedicated controllers normally used to control single process loops are being replaced by shared controllers which are ported with RTOS running multiple control algorithms parallelly. This work demonstrates a Cerebral Model Neural Network (CMNN) based control algorithm as a real time application in MPC8260 (PowerPC) embedded processor with VxWorks RTOS. Process signals from the sensors are interfaced to MPC8260 board through serial port and control signals given to the actuator are displayed on a client system running Hyper-Terminal application

A data dependency recovery system for a heterogeneous multicore processor

Multicore processors often increase the performance of applications. However, with their deeper pipelining, they have proven increasingly difficult to improve. In an attempt to deliver enhanced performance at lower power requirements, semiconductor microprocessor manufacturers have progressively utilised chip-multicore processors. Existing research has utilised a very common technique known as thread-level speculation. This technique attempts to compute results before the actual result is known. However, thread-level speculation impacts operation latency, circuit timing, confounds data cache behaviour and code generation in the compiler. We describe an software framework codenamed Lyuba that handles low-level data hazards and automatically recovers the application from data hazards without programmer and speculation intervention for an asymmetric chip-multicore processor. The problem of determining correct execution of multiple threads when data hazards occur on conventional symmetrical chip-multicore processors is a significant and on-going challenge. However, there has been very little focus on the use of asymmetrical (heterogeneous) processors with applications that have complex data dependencies. The purpose of this thesis is to: (i) define the development of a software framework for an asymmetric (heterogeneous) chip-multicore processor; (ii) present an optimal software control of hardware for distributed processing and recovery from violations;(iii) provides performance results of five applications using three datasets. Applications with a small dataset showed an improvement of 17% and a larger dataset showed an improvement of 16% giving overall 11% improvement in performance

A Framework to Model and Analyze the WHY and the HOW of Coopetition

Coopetition has been defined as an approach to managing that combines competition and cooperation. It transcends the traditional paradigms of competition and cooperation in an effort to achieve the advantages of both. As an inter-organizational relationship that is of a higher complexity than either simple competition or cooperation, coopetition presents both conceptual and practical challenges for business managers and researchers in the strategy field. In this paper we present a systemic approach to modeling coopetition between firms that provides a methodology for analyzing the strategic incentives for enterprises to engage in coopetition relationships and the organization design required to address the complexities inherent in such multi-faceted relationships. Our approach comprises a modeling technique called Systemic Enterprise Architecture Method (SEAM) that incorporates important conceptualizations adapted from competence based management (CBM) theory. We illustrate our approach by applying it to the case coopetition between IBM and Apple in the development of PowerPC CPU

Predictive control using an FPGA with application to aircraft control

Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) QP solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-inthe-loop testbench controlling a nonlinear simulation of a large airliner. This study considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a mid-range FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC