A SoC Design Methodology for LEON2 on FPGA

SoC design methodologies show up as a natural and productive method to implement embedded and/or ubiquitous systems. The authors explore the possibilities of the free LEON2 processor core, originally developed by the European Space Agency, and the Xilinx FPGA family to develop a complete SoC design methodology for both hardware and software. Advantages of the platform and productivity of the proposed methodology are highlighted through an application example, showing the suitability of LEON2 implemented on FPGA for professional-grade applications

Hybrid Linux System Modeling with Mixed-Level Simulation

Dissertação de mestrado integrado em Engenharia Electrónica Industrial e ComputadoresWe live in a world where the need for computer-based systems with better performances is growing fast, and part of these systems are embedded systems. This kind of systems are everywhere around us, and we use them everyday even without noticing. Nevertheless, there are issues related to embedded systems in what comes to real-time requirements, because the failure of such systems can be harmful to the user or its environment. For this reason, a common technique to meet real-time requirements in difficult scenarios is accelerating software applications by using parallelization techniques and dedicated hardware components. This dissertations’ goal is to adopt a methodology of hardware-software co-design aided by co-simulation, making the design flow more efficient and reliable. An isolated validation does not guarantee integral system functionality, but the use of an integrated co-simulation environment allows detecting system problems before moving to the physical implementation. In this dissertation, an integrated co-simulation environment will be developed, using the Quick EMUlator (QEMU) as a tool for emulating embedded software platforms in a Linux-based environment. A SystemVerilog Direct Programming Interface (DPI) Library was developed in order to allow SystemVerilog simulators that support DPI to perform co-simulation with QEMU. A library for DLL blocks was also developed in order to allow PSIMR to communicate with QEMU. Together with QEMU, these libraries open up the possibility to co-simulate several parts of a system that includes power electronics and hardware acceleration together with an emulated embedded platform. In order to validate the functionality of the developed co-simulation environment, a demonstration application scenario was developed following a design flow that takes advantage of the mentioned simulation environment capabilities.Vivemos num mundo em que a procura por sistemas computer-based com desempenhos cada vez melhores domina o mercado. Estamos rodeados por este tipo de sistemas, usando-os todos os dias sem nos apercebermos disso, sendo grande parte deles sistemas embebidos. Ainda assim, existem problemas relacionados com os sistemas embebidos no que toca aos requisitos de tempo-real, porque uma falha destes sistemas pode ser perigosa para o utilizador ou o ambiente que o rodeia. Devido a isto, uma técnica comum para se conseguir cumprir os requisitos de tempo-real em aplicações críticas é a aceleração de aplicações de software, utilizando técnicas de paralelização e o uso de componentes de hardware dedicados. O objetivo desta dissertação é adotar uma metodologia de co-design de hardwaresoftware apoiada em co-simulação, tornando o design flow mais eficiente e fiável. Uma validação isolada não garante a funcionalidade do sistema completo, mas a utilização de um ambiente de co-simulação permite detetar problemas no sistema antes deste ser implementado na plataforma alvo. Nesta dissertação será desenvolvido um ambiente de co-simulação usando o QEMU como emulador para as plataformas de software "embebido" baseadas em Linux. Uma biblioteca para SystemVerilog DPI foi desenvolvida, que permite a co-simulação entre o QEMU e simuladores de Register-Transfer Level (RTL) que suportem SystemVerilog. Foi também desenvolvida uma biblioteca para os blocos Dynamic Link Library (DLL) do PSIMR , de modo a permitir a ligação ao QEMU. Em conjunto, as bibliotecas desenvolvidas permitem a co-simulação de diversas partes do sistema, nomeadamente do hardware de eletrónica de potência e dos aceleradores de hardware, juntamente com a plataforma embebida emulada no QEMU.Para validar as funcionalidades do ambiente de co-simulação desenvolvido, foi explorado um cenário de aplicação que tem por base esse mesmo ambiente

Real-time linux and hardware accelerated systems on QEMU

Dissertação de mestrado integrado em Industrial Electronics Engineering and ComputersSoftware application acceleration, using parallelization techniques and dedicated hardware components, is often an optimization compromise in a cost-benefit relationship during the migration of software processes to hardware Intellectual Property (IP) dedicated cores or accelerators. In real-time applications extra care is needed when dealing with these issues, so that the real-time requirements of the application are not compromised. An isolated validation, as far as application domains are concerned, does not guarantee integral system functionality. Using an integrated co-simulation environment, chances of early system problem detection before moving to the physical implementation phase are improved. By adopting a design flow aided by co-simulation, not only is the development process sped up, but also resource independent, since the system can be developed in its entirety in a host platform without being bound to a physical target platform. This dissertation aims to adopt a methodology of hardware-software co-design aided by co-simulation and extend embedded system simulation techniques to hardware IP co-simulation and integral validation, improving the design process of hardware accelerated embedded systems in their various development phases. Using Quick EMUlator (QEMU) as a tool for emulating embedded software platforms in a Linux-based environment, modifications were idealized and developed to enable QEMU to extend its embedded software platform emulating capabilities for custom hardware co-processor development purposes. Two QEMU extensions were developed, enabling easy integration of behavioral devices and co-simulation with external Register-Transfer Level (RTL) models in QEMU’s target platforms. A Verilog PLI library was also developed to allow Verilog simulators that support PLI to perform co-simulation with QEMU. To demonstrate the capabilities of following a hardware-software embedded co-design using the developed simulation environment, a demonstration application scenario was developed following a design flow that takes advantage of said simulation environment possibilities.A aceleração de aplicações de software, utilizando técnicas de paralelização e componentes de hardware dedicados, é frequentemente um compromisso de optimização numa relação de custo-benefício durante a migração de processos de software para aceleradores ou cores hardware IP dedicados. Em aplicações real-time, cuidados extra são necessários ao lidar com estas problemáticas, de forma a que os requisitos real-time da aplicação não sejam comprometidos. Uma validação isolada, no que respeitam os vários domínios de aplicação, não garante uma funcionalidade integral do sistema. Utilizando um ambiente de co-simulação integrado, falhas no sistema podem ser detectadas numa fase inicial do projecto, antes de ser atingida uma fase de implementação física. Ao adoptar um design flow auxiliado por cosimulação, não só é o processo de desenvolvimento agilizado, mas também isento de dependências a nível da plataforma target, uma vez que o sistema pode ser desenvolvido inteiramente na plataforma host sem estar dependente dos recursos físicos associados uma plataforma target. Esta dissertação surge no âmbito da validação de uma metodologia de hardware-software co-design auxiliada por co-simulação, no extender de técnicas de simulação de sistemas embebidos, com ou sem aceleração de processos em hardware RTL, e na validação integral, aperfeiçoando o processo de design dos mesmos ao longo das várias fases de desenvolvimento. Utilizando o QEMU como ferramenta para emulação de ambientes baseados em Linux para plataformas de CPU+FPGA, alterações foram idealizadas e desenvolvidas para permitir extender as capacidades de emulação das mesmas no QEMU, para propósitos de desenvolvimento de aceleradores em hardware customizados, possibilitando a integração de devices comportamentais e co-simulação com modelos RTL externos nas plataformas target do QEMU. Para demonstrar as capacidades de seguir um co-design de hardware-software embebido utilizando o ambiente de simulação desenvolvido, um cenário de aplicação demonstrador foi desenvolvido seguindo um design flow que toma partido das possibilidades do referido ambiente de simulação

FPGA based reconfigurable body area network using Nios II and uClinux

This research is focused on identifying an appropriate design for a reconfigurable Body Area Network (BAN). In order to investigate the benefits and drawbacks of the proposed design, a BAN system prototype was built. This system consists of two distinct node types: a slave node and a master node. These nodes communicate using ZigBee radio transceivers. The microcontroller-based slave node acquires sensor data and transmits digitized samples to the master node. The master node is FPGA-based and runs uClinux on a soft-core microcontroller. The purpose of the master node is to receive, process and store digitized sensor data. In order to verify the operation of the BAN system prototype and demonstrate reconfigurability, a specific application was required. Pattern recognition in electrocardiogram (ECG) data was the application used in this work and the MIT-BIH Arrhythmia Database was used as the known data source for verification. A custom test platform was designed and built for the purpose of injecting data from the MIT-BIH Arrhythmia Database into the BAN system. The BAN system designed and built in this work demonstrates the ability to record raw ECG data, detect R-peaks, calculate and record R-R intervals, detect premature ventricular and atrial contractions. As this thesis will identify, many aspects of this BAN system were designed to be highly reconfigurable allowing it to be used for a wide range of BAN applications, in addition to pattern recognition of ECG data

Contract Testing for Reliable Embedded Systems

Embedded systems comprise diverse technologies complicating their design. By creating virtual prototypes of the target system, Electronic System Level Design, the early analysis of a system composed by electronics and software is possible. However, the concrete interaction between hardware modules and between hardware and software is left for late development stages and real prototype making. Generally, interaction between components is assumed to be correct. However, it has to be assumed on development implicitly because interaction between components is not considered in the functionality design. While single components are mostly thoroughly tested and guarantee certain reliability levels, their interaction is based on often underspecified interfaces. Although component usage is mostly specified, operational constraints are often left out. Finally, not only the interaction between components but also with the environment and the user are not ensured. Generally, only functional integration tests are executed and corner-cases are left out, leaving uncovered faults that only manifest as failures later when their cost is higher. Therefore, this work aims at component interaction through specification of interfaces, test generation and real-time test execution. The specification is based on the design-by-contract approach of software that specifies semantics of component interaction in addition to the syntactical definition through functions. In the first part of this work, a specification for the interaction between hardware modules is given. With the automatic real-time test execution, fulfillment of specified preconditions for correct component operation can be checked. In component-based design, the component is trusted and thus, its functionality is assumed to be correct when certain postconditions are specified. In a correct component assembly, component postconditions fulfill preconditions of other components resulting in an operational system. The specification of preconditions follows the definition of environmental properties, acceptable input sequences for interfacing pins, as well as acceptable signal parameters, such as voltage levels, slope times, delays and glitches. Postconditions are defined by the description of a functionality accompanying constraints, such as timing. These parameters are automatically determined on operation by a testing circuit. Parameters that violate the specification are signaled by the testing circuit and failure is detected. The chosen parameters can give hint of the reason for the failure being an evidence of a circuit fault. In the example of an Inter-Integrated Circuit (I2C) communication system, we define contracts and show comparisons between contract violation, fault categorization and failure occurrence under signal fault injection. To complete this work, support for fault analysis on the electronic system level design is given. For this, the data transfers between the high-level models used in the design are augmented with the defined contract parameters. With a specific interface, digital faults are generated for transactions with violating signal parameters that can be tracked by the system. This way, recovery mechanisms for synchronous communication are proposed and tested. In the second part, the interaction between hardware and software is tackled providing special methods for developing device drivers. For this, we do not only specify the interface between hardware and software but also map the hardware control elements to software, partially generating the software interface for a device. This is necessary because drivers handle devices with internal control elements like registers, data streams and interrupts that cannot be represented on software. This systematic composition of drivers facilitates the development of a device interface called the device mechanism. It is the lowest layer of a two-layer architecture for driver development. The device mechanism carries out the access to the device exporting a pure software interface. This interface is based on the device implementation being, thus, fully specified. Further data processing required for compliance with the operating system or application is carried out in the driver policy, the layer on top of it. With the definition of a software layer for device control, contracts specifying constraints of this interface are proposed. These contracts are based on implementation constraints of the device and on its dynamic behavior. Therefore, an extended finite state machine models the dynamic behavior of the device. Based on it, functions of the device mechanism can be augmented with preconditions on the state or on state machine variables. These conditions are then checked on runtime. After execution of a function, its postconditions are ensured, such as timing. This guarantees that different driver policies, operating systems or firmwares, use this same device mechanism fulfilling its constraints. On the example of a Philips webcam, we develop the complete driver for Linux based on our architecture, creating contracts for its device mechanism. Following the systematic composition and the contract approach, driver bugs are avoided that otherwise violate allowed values for device data and execution orders of device protocols

Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms

Nowadays many-core computing platforms are widely adopted as a viable solution to accelerate compute-intensive workloads at different scales, from low-cost devices to HPC nodes. It is well established that heterogeneous platforms including a general-purpose host processor and a parallel programmable accelerator have the potential to dramatically increase the peak performance/Watt of computing architectures. However the adoption of these platforms further complicates application development, whereas it is widely acknowledged that software development is a critical activity for the platform design. The introduction of parallel architectures raises the need for programming paradigms capable of effectively leveraging an increasing number of processors, from two to thousands. In this scenario the study of optimization techniques to program parallel accelerators is paramount for two main objectives: first, improving performance and energy efficiency of the platform, which are key metrics for both embedded and HPC systems; second, enforcing software engineering practices with the aim to guarantee code quality and reduce software costs. This thesis presents a set of techniques that have been studied and designed to achieve these objectives overcoming the current state-of-the-art. As a first contribution, we discuss the use of OpenMP tasking as a general-purpose programming model to support the execution of diverse workloads, and we introduce a set of runtime-level techniques to support fine-grain tasks on high-end many-core accelerators (devices with a power consumption greater than 10W). Then we focus our attention on embedded computer vision (CV), with the aim to show how to achieve best performance by exploiting the characteristics of a specific application domain. To further reduce the power consumption of parallel accelerators beyond the current technological limits, we describe an approach based on the principles of approximate computing, which implies modification to the program semantics and proper hardware support at the architectural level

MPSoCBench : um framework para avaliação de ferramentas e metodologias para sistemas multiprocessados em chip

Orientador: Rodolfo Jardim de AzevedoTese (doutorado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Recentes metodologias e ferramentas de projetos de sistemas multiprocessados em chip (MPSoC) aumentam a produtividade por meio da utilização de plataformas baseadas em simuladores, antes de definir os últimos detalhes da arquitetura. No entanto, a simulação só é eficiente quando utiliza ferramentas de modelagem que suportem a descrição do comportamento do sistema em um elevado nível de abstração. A escassez de plataformas virtuais de MPSoCs que integrem hardware e software escaláveis nos motivou a desenvolver o MPSoCBench, que consiste de um conjunto escalável de MPSoCs incluindo quatro modelos de processadores (PowerPC, MIPS, SPARC e ARM), organizado em plataformas com 1, 2, 4, 8, 16, 32 e 64 núcleos, cross-compiladores, IPs, interconexões, 17 aplicações paralelas e estimativa de consumo de energia para os principais componentes (processadores, roteadores, memória principal e caches). Uma importante demanda em projetos MPSoC é atender às restrições de consumo de energia o mais cedo possível. Considerando que o desempenho do processador está diretamente relacionado ao consumo, há um crescente interesse em explorar o trade-off entre consumo de energia e desempenho, tendo em conta o domínio da aplicação alvo. Técnicas de escalabilidade dinâmica de freqüência e voltagem fundamentam-se em gerenciar o nível de tensão e frequência da CPU, permitindo que o sistema alcance apenas o desempenho suficiente para processar a carga de trabalho, reduzindo, consequentemente, o consumo de energia. Para explorar a eficiência energética e desempenho, foram adicionados recursos ao MPSoCBench, visando explorar escalabilidade dinâmica de voltaegem e frequência (DVFS) e foram validados três mecanismos com base na estimativa dinâmica de energia e taxa de uso de CPUAbstract: Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before the definition of the final Multiprocessor System on Chip (MPSoC) architecture details. However, simulation can only be efficiently performed when using a modeling and simulation engine that supports system behavior description at a high abstraction level. The lack of MPSoC virtual platform prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools motivated us to develop the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with 1, 2, 4, 8, 16, 32, and 64 cores, cross-compilers, IPs, interconnections, 17 parallel version of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches). An important demand in MPSoC designs is the addressing of energy consumption constraints as early as possible. Whereas processor performance comes with a high power cost, there is an increasing interest in exploring the trade-off between power and performance, taking into account the target application domain. Dynamic Voltage and Frequency Scaling techniques adaptively scale the voltage and frequency levels of the CPU allowing it to reach just enough performance to process the system workload while meeting throughput constraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiency and performance, both for hardware and software components, we provided MPSoCBench features to explore dynamic voltage and frequency scalability (DVFS) and evaluated three mechanisms based on energy estimation and CPU usage rateDoutoradoCiência da ComputaçãoDoutora em Ciência da Computaçã

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

Σχεδιασμός και υλοποίηση αναδιαμορφούμενου ενσωματωμένου συστήματος μέτρησης αιθητήρων χωρητικότητας σε FPGA

Οι έξυπνοι αισθητήρες χρησιμοποιούνται όλο και πιο πολύ στις μέρες μας για την παρακολούθηση του περιβάλλοντος. Ουσιαστικά ένας έξυπνος αισθητήρας είναι ένα σύστημα το οποίο περιλαμβάνει εκτός από τα αισθητήρια και έναν επεξεργαστή ο οποίος παρέχει τη δυνατότητα τοπικής επεξεργασίας των μετρήσεων. Στο πλαίσιο της διπλωματικής εργασίας υλοποιήθηκε ένα έξυπνο και ευέλικτο ενσωματωμένο σύστημα για την μέτρηση αισθητήρων χωρητικότητας. Στο σύστημα εκτός από το κύκλωμα διεπαφής των αισθητήρων έχει ενσωματωθεί ένας επεξεργαστής LEON3 με τα απαραίτητα περιφερειακά και έχει εγκατασταθεί λειτουργικό σύστημα Linux. Η υλοποίηση έγινε σε FPGA της σειράς CYCLON της ALTERA στο αναπτυξιακό σύστημα της Terasic DE2-115. Για την μέτρηση των αισθητήρων έχει υλοποιηθεί ένα κύκλωμα διεπαφής το οποίο μετατρέπει της μεταβολές της χωρητικότητας σε μεταβολές συχνότητας με χρήση ενός ειδικά διαμορφωμένου ταλαντωτή δακτυλίου. Ακολούθως, χρησιμοποιείται ένας προγραμματιζόμενος μετρητής συχνότητας ο οποίος διαθέτει μεταβλητό χρονικό παράθυρο μέτρησης ώστε να παρέχει ευελιξία ως προς το χρόνο μέτρησης, την ακρίβεια και το εύρος των μετρούμενων συχνοτήτων. Το κύκλωμα διεπαφής έχει συνδεθεί στον εσωτερικό δίαυλο δεδομένων (AMBA bus) του επεξεργαστή LEON3 ώστε να συμπεριφέρεται ως ένα τυπικό περιφερειακό του επεξεργαστή και να επιτυγχάνεται εύκολη και αποδοτική διαχείρισή του από το λογισμικό της εφαρμογής. Στο δίαυλο AMBA έχουν συνδεθεί και άλλα περιφερειακά όπως για παράδειγμα μια SVGA οθόνη επαφής (touch screen), μια μονάδα δικτύου (ETHERNET) και ένα πληκτρολόγιο τα οποία προσδίδουν στο συνολικό σύστημα επιπλέον δυνατότητες και ευελιξία. Με το ενσωματωμένο λειτουργικό σύστημα Linux ο χρήστης του συστήματος μπορεί να χρησιμοποιεί ένα καθιερωμένο περιβάλλον για την επεξεργασία των μετρήσεων και την επικοινωνία με τους αισθητήρες. Ο χρήστης μπορεί να παρατηρεί τα αποτελέσματα στην SVGA οθόνη ή να εισάγει εντολές επεξεργασίας από το πληκτρολόγιο. Ταυτόχρονα υπάρχει η δυνατότητα απομακρυσμένης σύνδεσης με το σύστημα και μεταφοράς των αποτελεσμάτων σε ένα απομακρυσμένο υπολογιστή. Έχουν υλοποιηθεί προγράμματα σε γλώσσα C για την επεξεργασία των μετρήσεων και για τον έλεγχο του κυκλώματος διεπαφής. Ένα πρόγραμμα το οποίο υλοποιήθηκε αξιοποιεί την “touch screen” λειτουργία της οθόνης, ώστε να μην χρειάζεται απαραίτητα συνδεδεμένο πληκτρολόγιο στο σύστημα. Με το πρόγραμμα αυτό μπορεί να γίνει βαθμονόμηση του αισθητήρα και να υπολογίζεται η μέση τιμή και η διασπορά των μετρήσεων. Για να επαληθευθεί η ορθή λειτουργία του συστήματος ελήφθησαν μετρήσεις με χωρητικούς αισθητήρες αερίων οι οποίοι αποτελούνται από διαπλεκόμενα (interdigitated) ηλεκτρόδια και ένα στρώμα πολυμερούς, του οποίου οι ιδιότητες μεταβάλλονται με την απορρόφηση συγκεκριμένων αερίων. Η απόκριση του προτεινόμενου συστήματος για διάφορες συγκεντρώσεις αναλυτών συγκρίθηκε με τις μετρήσεις των ίδιων αισθητήρων με σύστημα γέφυρας και προέκυψε ικανοποιητική σύμπτωση. Η ευαισθησία του συστήματος είναι, επίσης, ικανοποιητική γιατί δίνει τη δυνατότητα μέτρησης πολύ μικρών μεταβολών της χωρητικότητας οι οποίες αντιστοιχούν σε μεταβολή μερικών δεκάδων Hz στη συχνότητα ταλάντωσης. Το σύστημα που υλοποιήθηκε μπορεί να χρησιμοποιηθεί σε πλήθος εφαρμογών και να προσαρμοστεί σε διαφορετικά περιβάλλοντα. Με την ενσωμάτωση του επεξεργαστή LEON3 ο οποίος είναι ευέλικτος και παραμετροποιήσιμος μπορούν να γίνουν εύκολα προσθήκες υλικού (hardware) και να προσαρμοστεί κατάλληλα το λογισμικό ώστε να προστεθούν επιπλέον λειτουργίες. Συνολικά, στην διπλωματική εργασία παρουσιάζεται ένα ευέλικτο, αυτόνομο, εύχρηστο και αποδοτικό “έξυπνο” σύστημα για την μέτρηση αισθητήρων χωρητικότητας, το οποίο περιλαμβάνει πολλαπλές λειτουργίες επεξεργασίας και επικοινωνίας και έχει πάρα πολλές δυνατότητες εξέλιξης. Η παρούσα υλοποίηση μπορεί να αποτελέσει οδηγό για παρόμοιες υλοποιήσεις στο μέλλον και παρουσιάζει τις προοπτικές των έξυπνων συστημάτων σε συνδυασμό με αισθητήρες.Smart sensors are used increasingly nowadays for environmental monitoring. A smart sensor is a system which includes apart from the sensor element a processor which enables local processing of the measurements. Within the framework of this master thesis a smart and flexible embedded system for measuring capacitance sensors has been designed and implemented. The system developed comprises of the sensor interface circuit, a LEON3 processor equipped with the necessary peripherals and a Linux operating system. The system implementation is done using a CYCLON series ALTERA FPGA, the Terasic DE2-115 development board and a custom board hosting the sensor elements. For the measurement of the sensors an interface circuit which converts the capacitance changes in frequency changes by using a specially designed ring oscillator is implemented. Subsequently, a programmable frequency counter featuring a variable measurement time window is used in order to provide flexibility to the measurement time, the accuracy and the range of elaborated frequencies. The interface circuit is connected to the internal data bus (AMBA bus) of LEON3 processor in order to behave as a typical peripheral of the processor and to achieve easy and efficient management from the application software. On the AMBA bus are also connected the standard peripherals of the system, namely, a SVGA touch screen display, a network module (ETHERNET) and a keyboard which give to the system additional capabilities and flexibility. With the embedded Linux operating system the system user can use a standard environment for the processing of the measurements and the communication with the sensors. The user can observe the results on the SVGA display or introduce editing commands from the keyboard. At the same time there is the possibility of a remote connection to the system and the transfer of the results to a remote computer. Programs written in the C programming language are developed for the processing of the measurements and the control of the interface circuit. A stand-allone system has been demonstrated exploiting the capabilities of the "touch screen" display mode and eliminating the need for the presence of a keyboard. The developed software module has the ability to perform sensor calibration and calculation of the mean value and the deviation of the measurements for all channels. To verify the system operation an array of four gas sensors has been used. The capacitive gas sensors consist of interdigitated electrodes and a polymer layer, whose electrical properties vary with the absorption of certain gases (analytes). The response of the proposed system compared to the capacitance measurements using a bridge for various concentrations of analytes has showed satisfactory agreement. The sensitivity of the system is also satisfactory as it can measure very small changes of capacitance resulting to a change of few tens of Hz in oscillation frequency. The system that was implemented can be used in numerous applications and can be adapted to various environments. By integrating the LEON3 processor which is flexible and configurable, hardware alterations can be easily made and the software can be adapted in order to add extra functionality. Overall, this thesis presents a flexible, stand-alone, easy-to-use and efficient smart system for the measurement of capacitive sensors, which includes multiple processing and communication functions and has many development possibilities. This implementation can be used as a guide for similar implementations in the future and shows the prospects of smart sensor systems