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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog frontend and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.Ministerio de EconomĂa y Empresa TEC2016-80923-
ECFA Detector R&D Panel, Review Report
Two special calorimeters are foreseen for the instrumentation of the very
forward region of an ILC or CLIC detector; a luminometer (LumiCal) designed to
measure the rate of low angle Bhabha scattering events with a precision better
than 10 at the ILC and 10 at CLIC, and a low polar-angle
calorimeter (BeamCal). The latter will be hit by a large amount of
beamstrahlung remnants. The intensity and the spatial shape of these
depositions will provide a fast luminosity estimate, as well as determination
of beam parameters. The sensors of this calorimeter must be radiation-hard.
Both devices will improve the e.m. hermeticity of the detector in the search
for new particles. Finely segmented and very compact electromagnetic
calorimeters will match these requirements. Due to the high occupancy, fast
front-end electronics will be needed. Monte Carlo studies were performed to
investigate the impact of beam-beam interactions and physics background
processes on the luminosity measurement, and of beamstrahlung on the
performance of BeamCal, as well as to optimise the design of both calorimeters.
Dedicated sensors, front-end and ADC ASICs have been designed for the ILC and
prototypes are available. Prototypes of sensor planes fully assembled with
readout electronics have been studied in electron beams.Comment: 61 pages, 51 figure
Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale
This work represents a power scalable pipelined ADC, which achieves low power variation depends upon the sampling rate and enables variation in throughput. The keys to power scalability at high sampling rates were current modulation-based architecture and the development of novel rapid power-on Op-amp, which can completely and quickly power on/off by the feedback approach. The result achieved in this design is as high as 50 Msps and as low as 1 ksps, keeping some important parameters of ADC as ENOB and SNDR are almost constant. Power variation in ADC has a flexible range from 7.5 ”W to 17 mW, which is lower power consumption than previous works
Digital implementation of the cellular sensor-computers
Two different kinds of cellular sensor-processor architectures are used nowadays in various
applications. The first is the traditional sensor-processor architecture, where the sensor and the
processor arrays are mapped into each other. The second is the foveal architecture, in which a
small active fovea is navigating in a large sensor array. This second architecture is introduced
and compared here. Both of these architectures can be implemented with analog and digital
processor arrays. The efficiency of the different implementation types, depending on the used
CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use
digital implementation rather than analog
A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications
International audienc
Hardware for digitally controlled scanned probe microscopes
The design and implementation of a flexible and modular digital control and data acquisition system for scanned probe microscopes (SPMs) is presented. The measured performance of the system shows it to be capable of 14-bit data acquisition at a 100-kHz rate and a full 18-bit output resolution resulting in less than 0.02-Ă
rms position noise while maintaining a scan range in excess of 1 ”m in both the X and Y dimensions. This level of performance achieves the goal of making the noise of the microscope control system an insignificant factor for most experiments. The adaptation of the system to various types of SPM experiments is discussed. Advances in audio electronics and digital signal processors have made the construction of such high performance systems possible at low cost
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