13 research outputs found

    Low-Density Parity-Check Coded High-order Modulation Schemes

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    In this thesis, we investigate how to support reliable data transmissions at high speeds in future communication systems, such as 5G/6G, WiFi, satellite, and optical communications. One of the most fundamental problems in these communication systems is how to reliably transmit information with a limited number of resources, such as power and spectral. To obtain high spectral efficiency, we use coded modulation (CM), such as bit-interleaved coded modulation (BICM) and delayed BICM (DBICM). To be specific, BICM is a pragmatic implementation of CM which has been largely adopted in both industry and academia. While BICM approaches CM capacity at high rates, the capacity gap between BICM and CM is still noticeable at lower code rates. To tackle this problem, DBICM, as a variation of BICM, introduces a delay module to create a dependency between multiple codewords, which enables us to exploit extrinsic information from the decoded delayed sub-blocks to improve the detection of the undelayed sub-blocks. Recent work shows that DBICM improves capacity over BICM. In addition, BICM and DBICM schemes protect each bit-channel differently, which is often referred to as the unequal error protection (UEP) property. Therefore, bit mapping designs are important for constructing pragmatic BICM and DBICM. To provide reliable communication, we have jointly designed bit mappings in DBICM and irregular low-density parity-check (LDPC) codes. For practical considerations, spatially coupled LDPC (SC-LDPC) codes have been considered as well. Specifically, we have investigated the joint design of the multi-chain SC-LDPC and the BICM bit mapper. In addition, the design of SC-LDPC codes with improved decoding threshold performance and reduced rate loss has been investigated in this thesis as well. The main body of this thesis consists of three parts. In the first part, considering Gray-labeled square M-ary quadrature amplitude modulation (QAM) constellations, we investigate the optimal delay scheme with the largest spectrum efficiency of DBICM for a fixed maximum number of delayed time slots and a given signal-to-noise ratio. Furthermore, we jointly optimize degree distributions and channel assignments of LDPC codes using protograph-based extrinsic information transfer charts. In addition, we proposed a constrained progressive edge growth-like algorithm to jointly construct LDPC codes and bit mappings for DBICM, taking the capacity of each bit-channel into account. Simulation results demonstrate that the designed LDPC-coded DBICM systems significantly outperform LDPC-coded BICM systems. In the second part, we proposed a windowed decoding algorithm for DBICM, which uses the extrinsic information of both the decoded delayed and undelayed sub-blocks, to improve the detection for all sub-blocks. We show that the proposed windowed decoding significantly outperforms the original decoding, demonstrating the effectiveness of the proposed decoding algorithm. In the third part, we apply multi-chain SC-LDPC to BICM. We investigate various connections for multi-chain SC-LDPC codes and bit mapping designs and analyze the performance of the multi-chain SC-LDPC codes over the equivalent binary erasure channels via density evolution. Numerical results demonstrate the superiority of the proposed design over existing connected-chain ensembles and over single-chain ensembles with the existing bit mapping design

    Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures

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    This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead

    On Complexity, Energy- and Implementation-Efficiency of Channel Decoders

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    Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity. In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. New exploration methodologies are presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. These exploration methodologies are based on efficiency trajectories rather than a single snapshot metric as done in state-of-the-art approaches.Comment: Submitted to IEEE Transactions on Communication

    Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

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    4 pagesInternational audienceFor high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques

    LTE Multicodeword-MIMO; Hybrid-ARQ performance studies

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    Langattomassa tiedonsiirrossa on tällä hetkellä meneillään suuria muutoksia, sitten ensimmäisen matkapuhelinsukupolven käyttöönoton. Uusia datapuhelimia, kuten myös kämmentietokoneita käytetään internetin selaamiseen, videoiden katselemiseen ja pelaamiseen matkapuhelinverkon kautta. Voidaakseen tyydyttämään kuluttajien vaatimukset, tarve uusien langattoman tiedonsiirron normien luomiseen on merkittävä. Long Term Evolution (LTE) on, Third Generation Partership Project:in (3GPP) johtama, ehdokas seuraavaksi matkapuhelinsukupolven standardiksi. LTE:n ominaisuuksiin kuuluvat mm. korkea suoritusteho, matala latenssi, yksinkertaisuus ja alhaiset kustannukset. Tulevassa standardissa on aihealueita, joita ei ole varsinaisesti tutkittu akateemisessa maailmassa kuten Hybrid Automatic Repeat Request:in (HARQ) suorituskykyä. Koska langaton tiedonsiirto on epälineaarinen prosessi, sitä mallinnetaan simulaattorin avulla. Simulaattori on tehty MATLAB ympäristössä LTE:n standardien mukaisesti. Kolme eri Multiple Input Multiple Output (MIMO) downlink HARQ skenaariota luotiin ja niiden suorituskykyä arvioitiin. Pääpaino työn tutkimukselle kohdistuu kolmen HARQ:n suorituskykyyn, tosin simulaattorimallin todistaminen on myös keskeinen osa tätä työtä.Mobile communication is going through major changes since the introduction of first generation mobile phones. Not only phones, but various handheld devices are starting to use the mobile communication network for internet browsing, multimedia or even online gaming. There is a high need for fast mobile connection and therefore new standards and specifications need to be created to satisfy the consumer requirements. Long Term Evolution (LTE) is the latest candidate for the next mobile communication standard led by Third Generation Partnership Project (3GPP). LTEs main features are high throughput, low latency, simple architecture and low operating costs. Since mobile data transmission is a non linear process, a simulator is built to model the procedure. Simulator made for this thesis was written in MATLAB meeting the 3GPPs set standards for LTE. Three different Multiple Input Multiple Output (MIMO) downlink HARQ scenarios were created and their performance was evaluated. The main focus of this thesis is the performance comparison of the three downlink scenarios; however the verification of the simulator model plays also a significant role in this work

    Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

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    This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.Comment: submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009

    VLSI Architectures for WIMAX Channel Decoders

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    This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.Comment: To appear in the book "WIMAX, New Developments", M. Upena, D. Dalal, Y. Kosta (Ed.), ISBN978-953-7619-53-
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