49 research outputs found

    Measuring the Phase Variation of a DOCSIS 3.1 Full Duplex Channel

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    Including a Full Duplex option into DOCSIS introduces several problems. One of the more troublesome issues is the presence of a strong self interference signal that leaks from the transmit side to the receive side of a cable node. This self interference is caused by echoes in the channel that translate the forward travelling transmit signals into a reverse travelling signal, as well as, by leakage from the hybrid coupler used to couple the upstream and downstream signals. To suppress this self interference an echo canceller is implemented to remove the unwanted interference from the received signal. Unfortunately with the high rates of data transmission used in modern day CATV networks the echo canceller needs tremendous precision. A major concern in the implementation of Full Duplex into DOCSIS is if the channels used are even very slightly time varying. The echos in such channels change with time and can be difficult for the echo canceller to track. Changes in the response of the channel cause the echo profile of the network to shift and the echo canceler to re-adapt to the new channel response. The issue with this changing response is that it is possible for the channel to change faster than the echo canceller can adapt, resulting in the interference becoming unacceptably high. Since the channel is a physical network of coaxial cables often exposed to the environment, its propagation properties can be affected by wind swaying pole mounted cables, or by rapid heating from the sun, or sudden shifts in the load of the network. With information on how the physical properties of the cable changes, the engineers designing the echo canceller can know how fast the canceller must adapt to changes and also have a better measure of how reliable its echo cancellation will be. In this thesis the stability of the echo profile of the channel is measured. It is shown that the property of the channel with the greatest potential to rapidly change and cause noise after echo cancellation is the phase response of the channel. Due to this, the approach of this thesis is to measure the fluctuations in the phase of the channel response of a CATV network constructed in the lab. To measure the fluctuations in the phase response of the channel, a PLL (Phase Locked Loop) based circuit is designed and built on an FPGA (Field Programmable Gate Array) and connected to a model of a simple CATV network. The PLL circuit used to measure the phase fluctuations of the channel is designed to be able to measure changes occurring faster than 0.1 Hz and with a power higher than 10−7 V210^{-7} \: V^2. The circuit is able to capture data from the channel over a period of 90 seconds. Using this phase variation measurement circuit a series of experiments were performed on a model CATV DOCSIS network. It was found that many physical disturbances to the network had the effect of rapidly shifting the phase response of the network. Heating the cables in the network was found to shift the phase response upwards of 20000 μ20000\:\muradians. Flexing the cables in the network was found to have a peak phase variation of 8000 μ8000\: \muradians with similar effects found from walking over cables. Overall, it was clear that physical effects on the network had the propensity to rapidly shift the network response. Any echo canceller that is designed in the future will have to consider these effects when reporting the cancellation that it is able to achieve

    Digital implementation of an upstream DOCSIS QAM modulator and channel emulator

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    The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century. At the dawn of the internet the dominant mode of access was through telephone lines. Despite advances in dial-up modem technology, the telephone system was unable to keep pace with the demand for data throughput. In the late 1990's an industry consortium known as Cable Television Laboratories, Inc. developed a standard protocol for providing high-speed internet access through the existing CATV infrastructure. This protocol is known as Data Over Cable Service Interface Specification (DOCSIS) and it helped to usher in the era of the information superhighway. CATV systems use different parts of the radio frequency (RF) spectrum for communication to and from the user. The downstream portion (data destined for the user) consumes the bulk of the spectrum and is located at relatively high frequencies. The upstream portion (data destined to the network from the user) of the spectrum is smaller and located at the low end of the spectrum. This lower frequency region of the RF spectrum is particularly prone to impairments such as micro-reflections, which can be viewed as a type of multipath interference. Upstream data transfer in the presence of these impairments is therefore problematic and requires complex signal correction algorithms to be employed in the receiver. The quality of a receiver is largely determined by how well it mitigates the signal impairments introduced by the channel. For this reason, engineers developing a receiver require a piece of equipment that can emulate the channel impairments in any permutation in order to test their receiver. The conventional test methodology uses a hardware RF channel emulator connected between the transmitter and the receiver under test. This method not only requires an expensive RF channel emulator, but a functioning analog front-end as well. Of these two problems, the expense of the hardware emulator is likely less important than the delay in development caused by waiting for a functional analog front-end. Receiver design is an iterative, time consuming process that requires the receiver's digital signal processing (DSP) algorithms be tested as early as possible to reduce the time-to-market. This thesis presents a digital implementation of a DOCSIS-compliant channel emulator whereby cable micro-reflections and thermal noise at the analog front-end of the receiver are modelled digitally at baseband. The channel emulator and the modulator are integrated into a single hardware structure to produce a compact circuit that, during receiver testing, resides inside the same field programmable gate array (FPGA) as the receiver. This approach removes the dependence on the analog front-end allowing it to be developed concurrently with the receiver's DSP circuits, thus reducing the time-to-market. The approach taken in this thesis produces a fully programmable channel emulator that can be loaded onto FPGAs as needed by engineers working independently on different receiver designs. The channel emulator uses 3 independent data streams to produce a 3-channel signal, whereby a main channel with micro-reflections is flanked on either side by adjacent channels. Thermal noise normally generated by the receiver's analog front-end is emulated and injected into the signal. The resulting structure utilizes 43 dedicated multipliers and 401.125 KB of RAM, and achieves a modulation error ratio (MER) of 55.29 dB

    An Efficient DOCSIS Upstream Equalizer

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    The advancement in the CATV industry has been remarkable. In the beginning, CATV provided a few television channels. Now it provides a variety of advanced services such as video on demand (VOD), Internet access, Pay-Per-View on demand and interactive TV. These advances have increased the popularity of CATV manyfold. Current improvements focus on interactive services with high quality. These interactive services require more upstream (transmission from customer premises to cable operator premises) channel bandwidth. The flow of data through the CATV network in both the upstream and downstream directions is governed by a standard referred to as the Data Over Cable Service Interface Specification (DOCSIS) standard. The latest version is DOCSIS 3.1, which was released in January 2014. The previous version, DOCSIS 3.0, was released in 2006. One component of the upstream communication link is the QAM demodulator. An important component in the QAM demodulator is the equalizer, whose purpose is to remove distortion caused by the imperfect upstream channel as well as the residual timing offset and frequency offset. Most of the timing and frequency offset are corrected by timing and frequency recovery circuits; what remains is referred to as offset. A DOCSIS receiver, and hence the equalizer within, can be implemented with ASIC or FPGA technology. Implementing an equalizer in an ASIC has a large nonrecurring engineering cost, but relatively small per chip production cost. Implementing equalizer in an FPGA has very low non-recurring cost, but a relatively high per chip cost. If the choice technology was based on cost, one would think it would depends only on the volume, but in practice that is not the case. The dominant factor when it comes to profit, is the time-to-market, which makes FPGA technology the only choice. The goal of this thesis is to design a cost optimized equalizer for DOCSIS upstream demodulator and implement in an FPGA. With this in mind, an important objective is to establish a relationship between the equalizer’s critical parameters and its performance. The parameter-performance relationship that has been established in this study revealed that equalizer step size and length parameters should be 1/64 and approximately 20 to yield a near optimum equalizer when considering the MER-convergence time trade-off. In the pursuit of the objective another relationship was established that is useful in determining the accuracy of the timing recovery circuit. That relationship establishes the sensitivity both of the MER and convergence time to timing offset. The equalizer algorithm was implemented in a cost effective manner using DSP Builder. The effort to minimize cost was focused on minimizing the number of multipliers. It is shown that the equalizer can be constructed with 8 multipliers when the proposed time sharing algorithm is implemented

    Converged wireline and wireless signal distribution in optical fiber access networks

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    Peak-to-Average Power Ratio Reduction of DOCSIS 3.1 Downstream Signals

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    Tone reservation (TR) is an attractive and widely used method for peak-to-average power ratio (PAPR) reduction of orthogonal frequency division multiplexing (OFDM) signals, where both transmitter and receiver agree upon a number of subcarriers or tones to be reserved to generate a peak canceling signal that can reduce the peak power of the transmitted signals. The tones are selected to be mutually exclusive with the tones used for data transmission, which allows the receiver to extract the data symbols without distortions. This thesis presents two novel PAPR reduction algorithms for OFDM signals based on the TR principle, which do not distort the transmitted signals. The first proposed algorithm is performed in the time domain, whereas the second algorithm is a new clipping-and-filtering method. Both algorithms consist of two stages. The first stage, which is done off-line, creates a set of canceling signals based on the settings of the OFDM system. In particular, these signals are constructed to cancel signals at different levels of maximum instantaneous power that are above a predefined threshold. The second stage, which is online and iterative, reduces the signal peaks by using the canceling signals constructed in the first stage. The precalculated canceling signals can be updated when different tone sets are selected for data transmission, accommodating many practical applications. Simulation results show that the proposed algorithms achieve slightly better PAPR reduction performance than the conventional algorithms. Moreover, such performance is achieved with much lower computational complexity in terms of numbers of multiplications and additions per iteration. Among the two proposed algorithms, the time-domain algorithm gives the best peak reduction performance but the clipping-and-filtering algorithm requires considerably less number of multiplications per iteration and can be efficiently implemented using the fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) structure

    Wavelength reconfigurability for next generation optical access networks

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    Next generation optical access networks should not only increase the capacity but also be able to redistribute the capacity on the fly in order to manage larger variations in traffic patterns. Wavelength reconfigurability is the instrument to enable such capability of network-wide bandwidth redistribution since it allows dynamic sharing of both wavelengths and timeslots in WDM-TDM optical access networks. However, reconfigurability typically requires tunable lasers and tunable filters at the user side, resulting in cost-prohibitive optical network units (ONU). In this dissertation, I propose a novel concept named cyclic-linked flexibility to address the cost-prohibitive problem. By using the cyclic-linked flexibility, the ONU needs to switch only within a subset of two pre-planned wavelengths, however, the cyclic-linked structure of wavelengths allows free bandwidth to be shifted to any wavelength by a rearrangement process. Rearrangement algorithm are developed to demonstrate that the cyclic-linked flexibility performs close to the fully flexible network in terms of blocking probability, packet delay, and packet loss. Furthermore, the evaluation shows that the rearrangement process has a minimum impact to in-service ONUs. To realize the cyclic-linked flexibility, a family of four physical architectures is proposed. PRO-Access architecture is suitable for new deployments and disruptive upgrades in which the network reach is not longer than 20 km. WCL-Access architecture is suitable for metro-access merger with the reach up to 100 km. PSB-Access architecture is suitable to implement directly on power-splitter-based PON deployments, which allows coexistence with current technologies. The cyclically-linked protection architecture can be used with current and future PON standards when network protection is required

    Timing Recovery for DOCSIS 3.1 Upstream OFDMA Signals

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    Data-Over-Cable Service Interface Specification (DOCSIS) is a global standard for cable communication systems. Before version 3.1, the standard has always specified single-carrier (SC) quadrature-amplitude modulation (QAM) as the modulation scheme. Given that the multi-carrier orthogonal frequency-division multiplexing (OFDM) technique has been increasingly popular and adopted in many wired/wireless communications systems, the newest cable communication standard, DOCSIS 3.1, also introduces OFDM as a major upgrade to improve transmission efficiency. In any digital communication systems, timing synchronization is required to determine and compensate for the timing offset from the transmitter to the receiver. This task is especially crucial and challenging in an OFDM system due to its very high sensitivity to synchronization errors. Although there have been many studies on the topic of OFDM timing synchronization, none of the existing methods are not directly applicable to DOCSIS 3.1 systems. Therefore, the main objective of this research is to develop effective and affordable timing synchronization algorithms for the DOCSIS 3.1 upstream signal. Specifically, three timing synchronization algorithms are proposed to comply and take advantage of the structure of the ranging signal (i.e., the signal used for synchronization purpose) specified in DOCSIS 3.1 standard. The proposed methods are evaluated under a realistic multipath uplink cable channel using computer simulation. The first algorithm makes use of the repetitive pattern of the symbol pairs in the ranging signal. The locations of the symbol pairs are determined by calculating a correlation metric and identifying its maximum value. The second and third algorithms are developed so that they exploit the mirrored symmetry of the binary phase-shift keying (BPSK)-modulated time-domain samples, corresponding to the first non-zero symbol in the ranging signal, and look for the exact location of the symmetry point. The first algorithm, with very low hardware complexity, provides reasonable performance under normal traffic and channel conditions. However its performance under a severe channel condition and heavy traffic is not satisfactory. The second and third algorithms provide much more accurate timing estimation results, even under the severe channel condition and heavy traffic flow. Since the second algorithm requires an enormous increase in hardware complexity, a few options are proposed to reduce the hardware complexity but it is still much higher than the complexity of the first algorithm. Applying the same complexity reduction techniques it is demonstrated that the third algorithm has similar hardware complexity to the first algorithm, while its timing estimation performance remains excellent
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