Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas

This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor is used, and a circuitry is implemented, which is able to extract the dynamic information from a single piezoresistive layer. The circuitry was inspired by structures found in human skin and retina, as they are biological systems made up of a dense network of receptors. It is largely based on an artificial retina , which is able to detect motion by using relatively simple spatial temporal dynamics. The circuitry was adapted to respond in the bandwidth of microvibrations produced by early slippage, resembling human skin. Experimental measurements from a chip implemented in a 0.35-mum four-metal two-poly standard CMOS process are presented to show both the performance of the building blocks included in each processing node and the operation of the whole system as a detector of early slippage.Ministerio de Economía y Competitividad TEC2006-12376-C02-01Gobierno de España TEC2006- 1572

Ultra-pure digital sideband separation at sub-millimeter wavelengths

Deep spectral-line surveys in the mm and sub-mm range can detect thousands of lines per band uncovering the rich chemistry of molecular clouds, star forming regions and circumstellar envelopes, among others objects. The ability to study the faintest features of spectroscopic observation is, nevertheless, limited by a number of factors. The most important are the source complexity (line density), limited spectral resolution and insufficient sideband (image) rejection (SRR). Dual Sideband (2SB) millimeter receivers separate upper and lower sideband rejecting the unwanted image by about 15 dB, but they are difficult to build and, until now, only feasible up to about 500 GHz (equivalent to ALMA Band 8). For example ALMA Bands 9 (602-720 GHz) and 10 (787-950 GHz) are currently DSB receivers. Aims: This article reports the implementation of an ALMA Band 9 2SB prototype receiver that makes use of a new technique called calibrated digital sideband separation. The new method promises to ease the manufacturing of 2SB receivers, dramatically increase sideband rejection and allow 2SB instruments at the high frequencies currently covered only by Double Sideband (DSB) or bolometric detectors. Methods: We made use of a Field Programmable Gate Array (FPGA) and fast Analog to Digital Converters (ADCs) to measure and calibrate the receiver's front end phase and amplitude imbalances to achieve sideband separation beyond the possibilities of purely analog receivers. The technique could in principle allow the operation of 2SB receivers even when only imbalanced front ends can be built, particularly at very high frequencies. Results: This digital 2SB receiver shows an average sideband rejection of 45.9 dB while small portions of the band drop below 40 dB. The performance is 27 dB (a factor of 500) better than the average performance of the proof-of-concept Band 9 purely-analog 2SB prototype receiver.Comment: 5 page

A Benes Based NoC Switching Architecture for Mixed Criticality Embedded Systems

Multi-core, Mixed Criticality Embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect becomes a potential point of uncertainty, introducing major challenges in proving behaviour is always within specified constraints, limiting the means of growing system performance to add more tasks, or provide more computational resources to existing tasks. We present MCENoC, a Network-on-Chip (NoC) switching architecture that provides innovations to overcome this with predictable, formally verifiable timing behaviour that is consistent across the whole NoC. We show how the fundamental properties of Benes networks benefit MCE applications and meet our architecture requirements. Using SystemVerilog Assertions (SVA), formal properties are defined that aid the refinement of the specification of the design as well as enabling the implementation to be exhaustively formally verified. We demonstrate the performance of the design in terms of size, throughput and predictability, and discuss the application level considerations needed to exploit this architecture

Neuro-fuzzy chip to handle complex tasks with analog performance

This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input–output delay, and precision, performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 um standard technology. It has two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided

Neuro-fuzzy chip to handle complex tasks with analog performance

This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

MISSED: an environment for mixed-signal microsystem testing and diagnosis

A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin

A Wireless Implantable System for Facilitating Gastrointestinal Motility.

Gastrointestinal (GI) electrical stimulation has been shown in several studies to be a potential treatment option for GI motility disorders. Despite the promising preliminary research progress, however, its clinical applicability and usability are still unknown and limited due to the lack of a miniaturized versatile implantable stimulator supporting the investigation of effective stimulation patterns for facilitating GI dysmotility. In this paper, we present a wireless implantable GI modulation system to fill this technology gap. The system consists of a wireless extraluminal gastrointestinal modulation device (EGMD) performing GI electrical stimulation, and a rendezvous device (RD) and a custom-made graphical user interface (GUI) outside the body to wirelessly power and configure the EGMD to provide the desired stimuli for modulating GI smooth muscle activities. The system prototype was validated in bench-top and in vivo tests. The GI modulation system demonstrated its potential for facilitating intestinal transit in the preliminary in vivo chronic study using porcine models

EndoTOFPET-US a Novel Multimodal Tool for Endoscopy and Positron Emission Tomography

The EndoTOFPET-US project aims to jointly exploit Time-Of-Flight Positron Emission Tomography (TOFPET) and ultrasound endoscopy with a multi-modal instrument for the development of new biomarkers for pancreas and prostate oncology. The paper outlines the functionality of the proposed instrument and the challenges for its realization. The high level of miniaturization and integration poses strong demands to the fields of scintillating crystallography, ultra-fast photon detection, highly integrated electronics and system integration. Solutions are presented to obtain a coincidence time resolution better than 200 ps and a spatial resolution of ~1 mm with an asymmetric TOFPET detector. A tracking system with better than 1 mm spatial resolution precision enables the online alignment of the system. The detector design, the production and test status of the single detecto