Resilient Pathways to Atomic Attachment of Quantum Dot Dimers and Artificial Solids from Faceted CdSe Quantum Dot Building Blocks.

The goal of this work is to identify favored pathways for preparation of defect-resilient attached wurtzite CdX (X = S, Se, Te) nanocrystals. We seek guidelines for oriented attachment of faceted nanocrystals that are most likely to yield pairs of nanocrystals with either few or no electronic defects or electronic defects that are in and of themselves desirable and stable. Using a combination of in situ high-resolution transmission electron microscopy (HRTEM) and electronic structure calculations, we evaluate the relative merits of atomic attachment of wurtzite CdSe nanocrystals on the {11̅00} or {112̅0} family of facets. Pairwise attachment on either facet can lead to perfect interfaces, provided the nanocrystal facets are perfectly flat and the angles between the nanocrystals can adjust during the assembly. Considering defective attachment, we observe for {11̅00} facet attachment that only one type of edge dislocation forms, creating deep hole traps. For {112̅0} facet attachment, we observe that four distinct types of extended defects form, some of which lead to deep hole traps whereas others only to shallow hole traps. HRTEM movies of the dislocation dynamics show that dislocations at {11̅00} interfaces can be removed, albeit slowly. Whereas only some extended defects at {112̅0} interfaces could be removed, others were trapped at the interface. Based on these insights, we identify the most resilient pathways to atomic attachment of pairs of wurtzite CdX nanocrystals and consider how these insights can translate to the creation of electronically useful materials from quantum dots with other crystal structures

Examining the Role of Chloride Ligands on Defect Removal in Imperfectly Attached Semiconductor Nanocrystals for 1D and 2D Attachment Cases

Semiconducting, core-shell nanocrystals (NCs) are promising building blocks for the construction of higher dimensional artificial nanostructures using oriented attachment. However, the assembly and epitaxial attachment steps critical to this construction introduce disorder and defects which inhibit the observation of desirable emergent electronic phenomena. Consequently, understanding defect formation and remediation in these systems as a function of dimensionality is a crucial step to perfecting their synthesis. In this work, we use in situ high resolution transmission electron microscopy to examine the role of chloride ligands as remediator agents for imperfect attachment interfaces between CdSe/CdS core-shell NCs for both 1D and 2D attachment cases. In the 1D case, we find that the presence of chloride additives in imperfectly attached NC dimers can result in defect removal speeds nearly twice as large as those found in their plain, non-chloride treated counterparts. However, when we increased the dimensionality of the system and examined 2D NC arrays, we found no statistically significant difference in attachment interface quality between the chloride and non-chloride treated samples. We propose that this discongruity arises from fundamental differences between 1D and 2D NC attachment and discuss synthetic guidelines to inform future nanomaterial superlattice design.Comment: 35 pages, 6 figures, work conducted at the University of California, Berkele

Transformations of High-Level Synthesis Codes for High-Performance Computing

Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS

On Characterizing the Data Access Complexity of Programs

Technology trends will cause data movement to account for the majority of energy expenditure and execution time on emerging computers. Therefore, computational complexity will no longer be a sufficient metric for comparing algorithms, and a fundamental characterization of data access complexity will be increasingly important. The problem of developing lower bounds for data access complexity has been modeled using the formalism of Hong & Kung's red/blue pebble game for computational directed acyclic graphs (CDAGs). However, previously developed approaches to lower bounds analysis for the red/blue pebble game are very limited in effectiveness when applied to CDAGs of real programs, with computations comprised of multiple sub-computations with differing DAG structure. We address this problem by developing an approach for effectively composing lower bounds based on graph decomposition. We also develop a static analysis algorithm to derive the asymptotic data-access lower bounds of programs, as a function of the problem size and cache size

A Survey of Positioning Systems Using Visible LED Lights

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.As Global Positioning System (GPS) cannot provide satisfying performance in indoor environments, indoor positioning technology, which utilizes indoor wireless signals instead of GPS signals, has grown rapidly in recent years. Meanwhile, visible light communication (VLC) using light devices such as light emitting diodes (LEDs) has been deemed to be a promising candidate in the heterogeneous wireless networks that may collaborate with radio frequencies (RF) wireless networks. In particular, light-fidelity has a great potential for deployment in future indoor environments because of its high throughput and security advantages. This paper provides a comprehensive study of a novel positioning technology based on visible white LED lights, which has attracted much attention from both academia and industry. The essential characteristics and principles of this system are deeply discussed, and relevant positioning algorithms and designs are classified and elaborated. This paper undertakes a thorough investigation into current LED-based indoor positioning systems and compares their performance through many aspects, such as test environment, accuracy, and cost. It presents indoor hybrid positioning systems among VLC and other systems (e.g., inertial sensors and RF systems). We also review and classify outdoor VLC positioning applications for the first time. Finally, this paper surveys major advances as well as open issues, challenges, and future research directions in VLC positioning systems.Peer reviewe

Beyond shared memory loop parallelism in the polyhedral model

2013 Spring.Includes bibliographical references.With the introduction of multi-core processors, motivated by power and energy concerns, parallel processing has become main-stream. Parallel programming is much more difficult due to its non-deterministic nature, and because of parallel programming bugs that arise from non-determinacy. One solution is automatic parallelization, where it is entirely up to the compiler to efficiently parallelize sequential programs. However, automatic parallelization is very difficult, and only a handful of successful techniques are available, even after decades of research. Automatic parallelization for distributed memory architectures is even more problematic in that it requires explicit handling of data partitioning and communication. Since data must be partitioned among multiple nodes that do not share memory, the original memory allocation of sequential programs cannot be directly used. One of the main contributions of this dissertation is the development of techniques for generating distributed memory parallel code with parametric tiling. Our approach builds on important contributions to the polyhedral model, a mathematical framework for reasoning about program transformations. We show that many affine control programs can be uniformized only with simple techniques. Being able to assume uniform dependences significantly simplifies distributed memory code generation, and also enables parametric tiling. Our approach implemented in the AlphaZ system, a system for prototyping analyses, transformations, and code generators in the polyhedral model. The key features of AlphaZ are memory re-allocation, and explicit representation of reductions. We evaluate our approach on a collection of polyhedral kernels from the PolyBench suite, and show that our approach scales as well as PLuTo, a state-of-the-art shared memory automatic parallelizer using the polyhedral model. Automatic parallelization is only one approach to dealing with the non-deterministic nature of parallel programming that leaves the difficulty entirely to the compiler. Another approach is to develop novel parallel programming languages. These languages, such as X10, aim to provide highly productive parallel programming environment by including parallelism into the language design. However, even in these languages, parallel bugs remain to be an important issue that hinders programmer productivity. Another contribution of this dissertation is to extend the array dataflow analysis to handle a subset of X10 programs. We apply the result of dataflow analysis to statically guarantee determinism. Providing static guarantees can significantly increase programmer productivity by catching questionable implementations at compile-time, or even while programming