Time-domain thru-reflect-line (TRL) calibration error assessment and its mitigation and modeling of multilayer printed circuit boards (PCB) with complex area fills

Part 1 for this thesis is on the error assessment of a time-domain (t-TRL) calibration technique. Application of the Thru-Reflect-Line (TRL) calibration to time-domain measurements of S-parameters (t-TRL) can be used for the characterization of the printed circuit boards (PCBs). However, t-TRL calibrated results still have deviations from the reference frequency-domain vector network analyzer (VNA) calibrated results. There are two main sources of errors in the t-TRL calibration. They are random errors, such as an additive noise and jitter, and systematic errors associated with cables, connectors, and port mismatches. This work addresses these two types of errors by proper selection of the number of sampling points, waveform averages, and time record. Methods tried out to eliminate or reduce these errors are detailed in this work. Measurements and simulations were performed for implementing these methods, and the results are explained. A t-TRL calibration automation tool based on TDR/TDT measurements has been developed. Part 2 of this thesis is on the modeling of multilayer PCBs with complex area fills and floating planes. Noise on the power distribution network (PDN) and between the power area fills in multilayer PCBs with complex geometries is a significant concern. Modeling of such PCBs can be done with a cavity model approach. Correlation of a 3D EM solver results with the Multilayer Via Transition Tool (MVTT) results based on cavity model is explained here. Additional modeling and validation was done using the equivalent inductance method --Abstract, page iii

High Frequency Devices and Circuit Modules for Biochemical Microsystems

This dissertation investigates high frequency devices and circuit modules for biochemical microsystems. These modules are designed towards replacing external bulky laboratory instruments and integrating with biochemical microsystems to generate and analyze signals in frequency and time domain. The first is a charge pump circuit with modified triple well diodes, which is used as an on-chip power supply. The second is an on-chip pulse generation circuit to generate high voltage short pulses. It includes a pulse-forming-line (PFL) based pulse generation circuit, a Marx generator and a Blumlein generator. The third is a six-port circuit based on four quadrature hybrids with 2.0~6.0 GHz operating frequency tuning range for analyzing signals in frequency domain on-chip. The fourth is a high-speed sample-and-hold circuit (SHC) with a 13.3 Gs/s sampling rate and ~11.5 GHz input bandwidth for analyzing signals in time domain on-chip. The fifth is a novel electron spin resonance (ESR) spectroscopy with high-sensitivity and wide frequency tuning range

High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques

While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mm² area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology

From analog to digital

Analog-to-digital conversion and its reverse, digital-to-analog conversion, are ubiquitous in all modern electronics, from instrumentation and telecommunication equipment to computers and entertainment. We shall explore the consequences of converting signals between the analog and digital domains and give an overview of the internal architecture and operation of a number of converter types. The importance of analog input and clock signal integrity will be explained and methods to prevent or mitigate the effects of interference will be shown. Examples will be drawn from several manufacturers' datasheets

Index to NASA Tech Briefs, 1974

The following information was given for 1974: (1) abstracts of reports dealing with new technology derived from the research and development activities of NASA or the U.S. Atomic Energy Commission, arranged by subjects: electronics/electrical, electronics/electrical systems, physical sciences, materials/chemistry, life sciences, mechanics, machines, equipment and tools, fabrication technology, and computer programs, (2) indexes for the above documents: subject, personal author, originating center