Modeling of Total Ionizing Dose Effects in Advanced Complementary Metal-Oxide-Semiconductor Technologies

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.Dissertation/ThesisPh.D. Electrical Engineering 201

Space and military radiation effects in silicon-on-insulator devices

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

STUDY OF RADIATION EFFECTS IN GAN-BASED DEVICES

Radiation tolerance of wide-bandgap Gallium Nitride (GaN) high-electron-mobility transistors (HEMT) has been studied, including X-ray-induced TID effects, heavy-ion-induced single event effects, and neutron-induced single event effects. Threshold voltage shift is observed in X-ray irradiation experiments, which recovers over time, indicating no permanent damage formed inside the device. Heavy-ion radiation effects in GaN HEMTs have been studied as a function of bias voltage, ion LET, radiation flux, and total fluence. A statistically significant amount of heavy-ion-induced gate dielectric degradation was observed, which consisted of hard breakdown and soft breakdown. Specific critical injection level experiments were designed and carried out to explore the gate dielectric degradation mechanism further. Transient device simulations determined ion-induced peak transient electric field and duration for a variety of ion LET, ion injection locations, and applied drain voltages. Results demonstrate that the peak transient electric fields exceed the breakdown strength of the gate dielectric, leading to dielectric defect generation and breakdown. GaN power device lifetime degradation caused by neutron irradiation is reported. Hundreds of devices were stressed in the off-state with various drain voltages from 75 V to 400 V while irradiated with a high-intensity neutron beam. Observing a statistically significant number of neutron-induced destructive single-event-effects (DSEEs) enabled an accurate extrapolation of terrestrial field failure rates. Nuclear event and electronic simulations were performed to model the effect of terrestrial neutron secondary ion-induced gate dielectric breakdown. Combined with the TCAD simulation results, we believe that heavy-ion-induced SEGR and neutron-induced SEGR share common physics mechanisms behind the failures. Overall, experimental data and simulation results provide evidence supporting the idea that both radiation-induced SBD and HBD are associated with defect-related conduction paths formed across the dielectric, in response to radiation-induced charge injection. A percolation theory-based dielectric degradation model is proposed, which explains the dielectric breakdown behaviors observed in heavy-ion irradiation experiments

Study of Radiation Tolerant Storage Cells for Digital Systems

Single event upsets (SEUs) are a significant reliability issue in semiconductor devices. Fully Depleted Silicon-on-Insulator (FDSOI) technologies have been shown to exhibit better SEU performance compared to bulk technologies. This is attributed to the thin Silicon (Si) layer on top of a Buried Oxide (BOX) layer, which allows each transistor to function as an insulated Si island, thus reducing the threat of charge-sharing. Moreover, the small volume of the Si in FDSOI devices results in a reduction of the amount of charge induced by an ion strike. The effects of Total Ionizing Dose (TID) on integrated circuits (ICs) can lead to changes in gate propagation delays, leakage currents, and device functionality. When IC circuits are exposed to ionizing radiation, positive charges accumulate in the gate oxide and field oxide layers, which results in reduced gate control and increased leakage current. TID effects in bulk technologies are usually simpler due to the presence of only one gate oxide layer, but FDSOI technologies have a more complex response to TID effects because of the additional BOX layer. In this research, we aim to address the challenges of developing cost-effective electronics for space applications by bridging the gap between expensive space-qualified components and high-performance commercial technologies. Key research questions involve exploring various radiation-hardening-by-design (RHBD) techniques and their trade-offs, as well as investigating the feasibility of radiation-hardened microcontrollers. The effectiveness of RHBD techniques in mitigating soft errors is well-established. In our study, a test chip was designed using the 22-nm FDSOI process, incorporating multiple RHBD Flip-Flop (FF) chains alongside a conventional FF chain. Three distinct types of ring oscillators (ROs) and a 256 kbit SRAM was also fabricated in the test chip. To evaluate the SEU and TID performance of these designs, we conducted multiple irradiation experiments with alpha particles, heavy ions, and gamma-rays. Alpha particle irradiation tests were carried out at the University of Saskatchewan using an Americium-241 alpha source. Heavy ion experiments were performed at the Texas A&M University Cyclotron Institute, utilizing Ne, Ar, Cu, and Ag in a 15 MeV/amu cocktail. Lastly, TID experiments were conducted using a Gammacell 220 Co-60 chamber at the University of Saskatchewan. By evaluating the performance of these designs under various irradiation conditions, we strive to advance the development of cost-effective, high-performance electronics suitable for space applications, ultimately demonstrating the significance of this project. When exposed to heavy ions, radiation-hardened FFs demonstrated varying levels of improvement in SEU performance, albeit with added power and timing penalties compared to conventional designs. Stacked-transistor DFF designs showed significant enhancement, while charge-cancelling and interleaving techniques further reduced upsets. Guard-gate (GG) based FF designs provided additional SEU protection, with the DFR-FF and GG-DICE FF designs showing zero upsets under all test conditions. Schmitt-trigger-based DFF designs exhibited improved SEU performance, making them attractive choices for hardening applications. The 22-nm FDSOI process proved more resilient to TID effects than the 28-nm process; however, TID effects remained prominent, with increased leakage current and SRAM block degradation at high doses. These findings offer valuable insights for designers aiming to meet performance and SER specifications for circuits in radiation environments, emphasizing the need for additional attention during the design phase for complex radiation-hardened circuits

Radiation Effects on CMOS Active Pixel Image Sensors

Today, Complementary-Metal-Oxide-Semiconductor (CMOS) Image Sensors (CIS), also called Active Pixel Sensors (APS), are the most popular imager technology with several billions manufactured every year. They represent about 90% of the imager market and should exceed 95% in a couple of years. Compared to the main alternative imager technology, the Charge Coupled Device (CCD), CISs have several major benefits such as low-power consumption, high-integration, high speed and the capacity to integrate advanced CMOS functions on-chip (and even inside the pixel). Thanks to the latest technology innovations, CISs are now matching the performances of CCDs in terms of image quality and sensitivity placing them at the forefront even in high-end applications such as digital single-lens reflex, scientific instruments, and machine vision. Thanks to these advantages, CISs are also used in harsh radiation environment for applications such as: space applications, X-ray medical imaging, electron microscopy, nuclear facility monitoring and remote handling (nuclear power plants, nuclear waste repositories, nuclear physics facilities…), particle detection and imaging, military applications etc.. Designing, hardening and testing a sensor for such applications require the understanding of the CIS behavior when exposed to radiation sources. Understanding and improving further the intrinsically good radiation hardness of APS has been a topic of interest since its invention. This interest has been recently growing with the coming of new behaviors brought by the profound evolution of CIS technologies (as discussed throughout this manuscript) compared to the older generation mainstream CMOS processes used in early work. The aim of this chapter is to give an overview of the parasitic effects that can undergo a modern CIS when it is exposed to a high energy particle radiation field

Journal of Telecommunications and Information Technology, 2001, nr 1

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