Array Phase Shifters: Theory and Technology

Phase shifters are linear one- or two-port devices for adjusting the reflection or insertion carrier phase of a band-limited signal, nominally from 0 to 2 radians. A perfect phase shifter would have: no insertion loss, a voltage standing wave ratio of 1:1, arbitrarily high power handling capability, linear phase-versus-frequency response, an arbitrarily small footprint, radiation immunity, no DC power consumption, and of course be free. Remarkably, real phase shifters can approach some of these idealized attributes. New processing techniques hold promise to significantly reduce manufacturing cost (see "Trends" at the end of this chapter)

Two-Dimensional Electronics - Prospects and Challenges

During the past 10 years, two-dimensional materials have found incredible attention in the scientific community. The first two-dimensional material studied in detail was graphene, and many groups explored its potential for electronic applications. Meanwhile, researchers have extended their work to two-dimensional materials beyond graphene. At present, several hundred of these materials are known and part of them is considered to be useful for electronic applications. Rapid progress has been made in research concerning two-dimensional electronics, and a variety of transistors of different two-dimensional materials, including graphene, transition metal dichalcogenides, e.g., MoS2 and WS2, and phosphorene, have been reported. Other areas where two-dimensional materials are considered promising are sensors, transparent electrodes, or displays, to name just a few. This Special Issue of Electronics is devoted to all aspects of two-dimensional materials for electronic applications, including material preparation and analysis, device fabrication and characterization, device physics, modeling and simulation, and circuits. The devices of interest include, but are not limited to transistors (both field-effect transistors and alternative transistor concepts), sensors, optoelectronics devices, MEMS and NEMS, and displays

Electronic and spintronic devices using two-dimensional materials

179 p. El contenido del capítulo 8 está sujeto a confidencialidadEver since in 2004 atomically-thin two-dimensional van der Waals materials became available to the scientific community, at the reach of manual microexfoliation techniques, their implementation in novel device structures and concepts promised disruptive new applications and motivated research in a vast range of fields.Confined to the thinnest possible thickness, electrons in these materials exhibit a plethora of electronic properties, from semiconducting MoS2, to superconductor NbSe2, dielectric BN, and, jack-of-all trades, graphene.In this thesis, we explore fundamental and applied aspects of chemical vapor deposition (CVD) graphene, MoS2, and WSe2 using electronic device structures that use them as transporting channel, namely field-effect transistors (FETs), Hall bars, and diodes.MoS2 is a n-type semiconducting 2D vdW that complements one of the weak aspects of graphene-based transistors, which is the small ratio between the maximum current output and of the minimum current output of the transistors. Using MoS2 we identify an electron doping constraint for performing stable magnetotransport measurements, and we investigate the origins of the strong current fluctuations of the FETs. We study the low-frequency noise (LFN) of the current output of devices made with different layer thicknesses, and use the strong light-matter interactions of MoS2 to employ photodoping techniques together with the electrostatic gating to dope the channel. By converging all these conditions, we are able to discern the mechanism behind the different types of LFN noise reported in literature for MoS2, while at the same time identifying a LFN crossover driven by photodoping.With p-type semiconducting WSe2 we optimize the electron and hole transport properties of ambipolar FETs by considering BN as a top and bottom interface substrate and encapsulation layer, respectively. By doing so, we areable to address to some extent the strong hysteretic effects that adversely affect the operation of WSe2 FETs on oxide substrates, and improve the overall device performance.The versatility of CVD graphene allows us to do both applied and fundamental studies, both related to spintronics and electronics.The unique properties of graphene make it a core material in the search of full-electrical approaches to generate, transport, and detect spin currents without the use of magnetic elements. Using a Hall-bar shaped sample, non-local signals in graphene have been demonstrated to be associated with spin transport. In our case, we use the large area availability of CVD graphene to study non-local effects in an unlikely scenario for the transport of spins. We study the non-local signals of millimeter sized Hall-bars of CVD graphene, and by doing a systematic study as a function of device scale, from macro-to-microscale we identify a mechanism that cannot be connected with spin diffusion that also leads to large signals. By evaluating the microscopic details of the samples, and the different effects observed, we propose a mechanism mediated by grain boundaries to drive such effects.In a more applied manner, we use CVD graphene for two other types of devices. First, we study the use of graphene as an electrode material for lateral and vertical field-effect transistors that operate using organic channels, and determine that the low density of states of graphene allows for unscreened electric fields to reach the organic layer and enable the transistor operation in the vertical geometry.The second applied study is the large-scale fabrication of diodes using CVD graphene. Benefiting from the ultra-thin cross section of graphene, and using a lateral geometry we demonstrate the reliable fabrication of lateral metal/insulator/graphene diodes. The time constants determined from the direct-current analysis place the operation of the fabricated devices in the THz range. Additionally, the material combination considered enabled large current densities based on field-emission processes.CICnanoGUNE : nanoscience cooperative research cente

대면적 그래핀의 전자기파 흡수 및 가스 배리어 특성과 스마트 어플리케이션에의 응용 연구

학위논문 (박사)-- 서울대학교 대학원 : 자연과학대학 화학부, 2019. 2. 홍병희.Graphene is an atomically thin carbon material with a two-dimensional hexagonal lattice that shows outstanding electrical and mechanical properties as well as excellent biocompatibility. Thanks to its outstanding electrical property, graphene can be utilized as very high performance electromagnetic (EM) wave shielding materials with extreme thin and transparent, light-weight. It is reported that ideal graphene can block as much as 97.8% of EMI. Also, It is reported that the monolayer graphene synthesized by CVD has an average SE value of 2.27dB, corresponding to 40% shielding, presenting 7 times (in terms of dB) greater SE than gold film. In addition, small gas molecules cannot pass through graphene, because its densely packed hexagonal lattice structure of carbon atoms. In these reasons, I believe that graphene is the most suitable materials to realize such smart electronics (wearable contact lens device, heater for automobile, so on) We report a CVD graphene-based highly conducting contact lens platform that reduces the exposure to EM waves and dehydration. Additionally, we demonstrate simple contact lens platform micro LED operating devices fabricated by CVD graphene-based conductive layers. Thus, we believe that the graphene-coated contact lens would provide a healthcare and bionic platform for wearable technologies in the future. We also demonstrate EM wave shielding mechanism of graphene. Graphene generate a heat energy as a result of EM wave shielding. Therefore, this allows graphene heater to be used widely in fields of automobile defogging/deicing systems, smart heating windows and EM-wave detecting sensors.탄소 원자가 2차원 방향으로 육각 격자 구조를 이루고 있는 그래핀은 뛰어난 기계적, 전기적 특성 뿐 아니라 생체친화적인 재료로 알려져 있다. 뛰어난 전기적 특성 때문에 그래핀은 가볍고 투명하면서도 매우 우수한 전자기 차폐 재질로 활용 될 수 있다. 구조적인 결함이 없는 이상적인 그래핀은 97.8%의 전자기 차폐 특성을 구현 할 수 있다고 보고 되고 있다. 실험적으로는 그래핀을 대면적으로 합성 할 수 있는 CVD법으로 제작 한 그래핀에서 모노레이어 기준으로 40%의 전자기 차폐 효과를 얻을 수 있고, 이는 단위 두께로 환산 시 금 박막과 비교하여 7배에 해당하는 수치이다. 또한 그래핀은 탄소 원자가 육각형의 안정적인 구조로 밀집 해 있어 가스 투과를 차단하는 특성도 가지고 있다. 이렇듯 그래핀은 가볍고, 투명하며 생체친화적인 재질에다 전기적, 기계적 특성이 우수하여, 최근 각광 받고 있는 스마트 일렉트로닉스를 구현하는데 있어 가장 적합한 재료로 판단 된다. 이 논문에서는 CVD 그래핀의 우수한 전자기파 차폐 및 가스 투과 차단 특성을 이용하여, 그래핀이 코팅 된 컨택트 렌즈에서 전자파 차폐 및 안구 건조를 방지하는 효과기 있음을 간접적인 방법으로 증명 하였다. 또한 컨택트 렌즈 위에 그래핀을 정밀 패턴하고 간단한 Micro LED Device를 제작 함으로서 그래핀을 스마트 컨택트 렌즈를 구현하는데 있어 다양한 용도의 물질로 활용 할 수 있음을 보였다. 또한 CVD 그래핀의 EM 차폐 메커니즘이 그래핀의 높은 전자이동도 및 반자성 특성 때문이라는 것을 증명 하였다. 그래핀의 전자파 차폐 과정에서 열 에너지가 효율적으로 발생되는 것을 이용하여 차량용 방습 히터 등의 어플리케이션으로 활용 가능성을 보였다.Abstract 1 Contents 3 List of Figures 5 1. General Introduction 1.1 Graphene 13 1.2 Graphene Synthesis 23 1.3 Scope of the Thesis 34 1.4 References 35 2. Smart Contact Lenses with Graphene Coating for Electro Magnetic Interference Shielding and Dehydration Protection 2.1 INTRODUCTION 40 2.2 RESULTS AND DISCUSSION 42 2.3 CONCLUSIONS 53 2.4 EXPERIMENTAL SECTION 54 2.5 REFERENCES 61 3. Efficient heat generation in large-area graphene films by electromagnetic wave absorption 3.1 INTRODUCTION 66 3.2 RESULTS AND DISCUSSION 68 3.3 CONCLUSION 78 3.4 EXPERIMENTAL SECTION 79 3.5 REFERENCES 87 Appendix (List of Publications) 92 Abstract (Korean) 93 Acknowledgement (Korean) 95Docto

Graphene transistors for radio frequency applications

Dissertação de mestrado integrado em Engenharia Física (área de especialização em Dispositivos, Microssistemas e Nanotecnologias)O grafeno atraiu imensa atenção devido à alta mobilidade dos portadores de carga, tornando um potencial novo material para eletrónica de radio frequência. Transístores fabricados com grafeno, fabricados até à data, possuem frequência de corte intrínsecas de 427 GHz. O fabrico de transístores de grafeno para aplicações de radiofrequência é dificultado devido às tecnologias de fabrico CMOS não poderem ser usadas, no seu estado atual, para este novo material. Neste trabalho, uma deposição física da porta e do óxido da porta foi escolhida de forma a minimizar os danos causados à rede de grafeno e um processo de auto alinhamento para reduzir as resistências de contacto. De forma a maximizar as figuras de mérito das estruturas pretendidas, foram feitas simulações que correlacionam os parâmetros físicos do dispositivo com as figuras de mérito. Os resultados obtidos dessas simulações mostraram que a elevada discrepância entre as figuras de mérito intrínsecas e extrínsecas resultam do elevado rácio entre as capacitâncias da porta dreno e porta-fonte para as capacitâncias parasíticas da porta e do dreno. Um aumento da camada de passivação e redução dos pads resultam na redução significativa do rácio entre os dois. As simulações também mostraram que reduzindo as resistências, capacidades e indutâncias parasitas resulta numa melhoria das figuras de mérito. A redução da largura do canal e aumento do comprimento do canal resulta no aumento das figuras de mérito intrínsecas e consequentemente as extrínsecas. O grafeno foi crescido por CVD numa folha de cobre, que produz alta qualidade e grandes áreas, e transferido para um substrato isolador. Nano-fios de níquel foram crescidos por deposição eletroquímica usando estruturas de oxido de alumínio anodizado (AAO) com uma camada de semente fina de ouro e uma mistura de NiSO4, NiCl2 e H3BO3, produziram nano-fios com diâmetros entre 200 e 400 nm. A estrutura foi removida com uma solução de NaOH, expondo os nano-fios. A cobertura dos nano-fios foi realizada através da oxidação do níquel e deposição de dióxido de silício. Ambas estas estruturas de núcleo-concha foram utilizadas na fabricação dos transístores. Os nano-fios núcleo-concha foram libertados da camada semente com uma solução de KI e I2, e subsequentemente aleatoriamente posicionados em cima do grafeno. Imagens de alta resolução foram obtidas da exata posição dos nano-fios e com a ajuda de marcadores de Titânio- Tungstênio (TiW), previamente depositados, mascaras para os processos litográficos foram desenhadas, estabelecendo um comprimento do canal em 3 μm. O processo de auto alinhamento foi por fim usado para depositar os contactos do dreno e fonte (Cr/Pd), alinhando-os perfeitamente e reduzindo a resistência de contacto por consequência. Um processo dieletroforético foi também desenvolvido para posicionar precisamente os nano-fios no substrato e possibilitar a escalabilidade do processo de fabrico. Por último, caracterização dos dispositivos fabricados foi realizada. Os dispositivos fabricados na primeira iteração mostraram baixo isolamento entre a porta e o canal, sendo esta atribuída ao dielétrico escolhido. Os dispositivos da segunda iteração do processo de fabrico foram impossíveis de caracterizar eletricamente devido à falta de conexão elétrica após a primeira ligação das sondas de medição.Graphene has attracted an immense amount of attention due to its high carrier mobility, making it a potentially new material for radio-frequency electronics. Transistors fabricated with graphene have reached intrinsic cut-off frequencies of 300 GHz. The fabrication of graphene RF transistors is challenging as most of the standard CMOS technologies cannot be employed in their current state to this new material. In this work, a physical deposition of the gate and gate oxide was chosen to minimize the damages to the graphene lattice and a self-aligned process to reduce the contact resistance. In order to maximize the figures of merit of the intended structure, simulations were made correlating the physical parameters to the figures of merit. Results obtained from these simulations showed that the high discrepancy between intrinsic and extrinsic figures of merit resulted from the high ratio between the gate-drain and gate-source capacitances to the parasitic gate and drain parasitic capacitances. An increase in the passivation layer and reduction of the gate and drain pads results in a significantly lower ratio between the two. Simulations also showed that, by minimizing the parasitic resistances, capacitances and inductances results in the increase of both intrinsic and extrinsic figures of merit. Reduction of the channel length and increase of the channel width results in the increase of the intrinsic, and subsequently extrinsic, figures of merit. Graphene was grown by CVD on a copper foil, which yielded high quality and large area graphene, and transferred onto the insulating substrate. Nickel nanowires were grown by electrochemical deposition using an Anodized Aluminum Oxide (AAO) template with a gold seed layer and a mixture of NiSO4, NiCl2 and H3BO3, resulting in nanowires with diameters ranging from 200 to 400 nanometers. The template was removed with a solution of NaOH creating free standing nanowires. Coating of the nanowires was performed through the oxidation of nickel and deposition of silicon dioxide. Both of these types of core-shell nanowires were used in the fabrication of the transistors. The core-shell nanowires were released from the seed layer with a solution of KI and I2 and subsequently randomly placed on top of the graphene. High resolution images of the nanowires precise position were taken and with the aid of Titanium-Tungsten (TiW) markers previously deposited, masks for a lithographic process were designed, setting the channel width to 3 μm. A self-aligned process was lastly employed to deposit the Drain-Source contacts (Cr/Pd), perfectly aligning them and in turn, greatly reducing the access resistance. A dielectrophoretic method was also developed to perfectly position the nanowires on the substrate and in turn scale up the device fabrication process. Lastly, characterization of the fabrication took place. Devices fabricated on the first run of the experiment showed poor isolation between the gate and channel of the devices. This was attributed to the dielectric choice. The second set of fabricated devices were unable to be characterized as connections made onto the devices failed to provide electrical contact after the first placement of the measuring probes

The modification of surfaces : from fundamentals to applications

You’re surrounded by surfaces. Viewed from a macro perspective they might appear soft, brightly colored, or textured. Maybe you don’t think anything of them at all. But what happens when we take a closer look? Here, down at the nanoscale, chemical reactions at surfaces play a hugely important role in the world in which we live. Whether it’s preventing metal corrosion, or developing the latest fuel cell, the state of surface being investigated is crucial. Indeed, by intentionally modifying surfaces we can introduce desirable properties, all because we’re controlling what goes on at the molecular level. The first part of this thesis discusses the use of model surfaces to probe fundamental properties and processes. Firstly, model surfaces displaying well-defined chemical functionality are created using self-assembled monolayers (SAMs), and are subsequently used as a means to understand the primary interactions that occur between carbonaceous soot contaminants, and surfactant-like molecules in engine oils. The quartz-crystal microbalance (QCM) is employed as a means to determine minute levels of surface adsorption, and a structure-activity relationship for these molecules is suggested. Next, a new approach for profiling the activity of molecular adsorbates at carbon surfaces is introduced, which allows for the impact of individual surface features on resulting electrochemical activity to be determined. It is used to study the case of quinone adsorption at graphite electrodes, a currently debated topic, and it is revealed that current literature models regarding the activity of the basal surface need revision, with significant implications for carbon electrochemistry as a whole. The second part of this thesis turns to understanding and controlling surface modification processes. Through a range of complementary techniques, the ability of scanning electrochemical cell microscopy (SECCM) to control the extent of the aryl diazonium grafting process at sp2 carbon surfaces is demonstrated. Aryl diazonium chemistry as been identified as a route to band-gap generation in graphene electronics, and as such, controlled routes to localized surface modification are of great interest. Next, the versatility of SECCM for controlled surface modification is further demonstrated, where it is used as a method to draw intricate patterns of defined surface chemistry in graphene, with a strong focus on the production of integrated graphene circuits, a prospect often promised. Finally, a new methodology for the transfer of graphene synthesized via chemical vapor deposition (CVD) is introduced. Crucially, it yields graphene surfaces with distinctly low levels of contamination, an area that currently poses a problem in graphene research

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Electronic and spintronic devices using two-dimensional materials

179 p. El contenido del capítulo 8 está sujeto a confidencialidadEver since in 2004 atomically-thin two-dimensional van der Waals materials became available to the scientific community, at the reach of manual microexfoliation techniques, their implementation in novel device structures and concepts promised disruptive new applications and motivated research in a vast range of fields.Confined to the thinnest possible thickness, electrons in these materials exhibit a plethora of electronic properties, from semiconducting MoS2, to superconductor NbSe2, dielectric BN, and, jack-of-all trades, graphene.In this thesis, we explore fundamental and applied aspects of chemical vapor deposition (CVD) graphene, MoS2, and WSe2 using electronic device structures that use them as transporting channel, namely field-effect transistors (FETs), Hall bars, and diodes.MoS2 is a n-type semiconducting 2D vdW that complements one of the weak aspects of graphene-based transistors, which is the small ratio between the maximum current output and of the minimum current output of the transistors. Using MoS2 we identify an electron doping constraint for performing stable magnetotransport measurements, and we investigate the origins of the strong current fluctuations of the FETs. We study the low-frequency noise (LFN) of the current output of devices made with different layer thicknesses, and use the strong light-matter interactions of MoS2 to employ photodoping techniques together with the electrostatic gating to dope the channel. By converging all these conditions, we are able to discern the mechanism behind the different types of LFN noise reported in literature for MoS2, while at the same time identifying a LFN crossover driven by photodoping.With p-type semiconducting WSe2 we optimize the electron and hole transport properties of ambipolar FETs by considering BN as a top and bottom interface substrate and encapsulation layer, respectively. By doing so, we areable to address to some extent the strong hysteretic effects that adversely affect the operation of WSe2 FETs on oxide substrates, and improve the overall device performance.The versatility of CVD graphene allows us to do both applied and fundamental studies, both related to spintronics and electronics.The unique properties of graphene make it a core material in the search of full-electrical approaches to generate, transport, and detect spin currents without the use of magnetic elements. Using a Hall-bar shaped sample, non-local signals in graphene have been demonstrated to be associated with spin transport. In our case, we use the large area availability of CVD graphene to study non-local effects in an unlikely scenario for the transport of spins. We study the non-local signals of millimeter sized Hall-bars of CVD graphene, and by doing a systematic study as a function of device scale, from macro-to-microscale we identify a mechanism that cannot be connected with spin diffusion that also leads to large signals. By evaluating the microscopic details of the samples, and the different effects observed, we propose a mechanism mediated by grain boundaries to drive such effects.In a more applied manner, we use CVD graphene for two other types of devices. First, we study the use of graphene as an electrode material for lateral and vertical field-effect transistors that operate using organic channels, and determine that the low density of states of graphene allows for unscreened electric fields to reach the organic layer and enable the transistor operation in the vertical geometry.The second applied study is the large-scale fabrication of diodes using CVD graphene. Benefiting from the ultra-thin cross section of graphene, and using a lateral geometry we demonstrate the reliable fabrication of lateral metal/insulator/graphene diodes. The time constants determined from the direct-current analysis place the operation of the fabricated devices in the THz range. Additionally, the material combination considered enabled large current densities based on field-emission processes.CICnanoGUNE : nanoscience cooperative research cente

The 3rd International Conference on the Challenges, Opportunities, Innovations and Applications in Electronic Textiles

This reprint is a collection of papers from the E-Textiles 2021 Conference and represents the state-of-the-art from both academia and industry in the development of smart fabrics that incorporate electronic and sensing functionality. The reprint presents a wide range of applications of the technology including wearable textile devices for healthcare applications such as respiratory monitoring and functional electrical stimulation. Manufacturing approaches include printed smart materials, knitted e-textiles and flexible electronic circuit assembly within fabrics and garments. E-textile sustainability, a key future requirement for the technology, is also considered. Supplying power is a constant challenge for all wireless wearable technologies and the collection includes papers on triboelectric energy harvesting and textile-based water-activated batteries. Finally, the application of textiles antennas in both sensing and 5G wireless communications is demonstrated, where different antenna designs and their response to stimuli are presented