Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW1, using 1.2 V supply. The two LNA approaches proposed in this thesis are validated by simulation and by measurement results, and are included in a receiver front-end for biomedical applications (ISM and WMTS), as an example; however, they have a wider range of applications

Design of broadband CNFET LNA based on extracted I-V closed-form equation

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A procedure of extracting a closed-form user-friendly I-V equation for short channel carbon nanotube field-effect transistors (CNFET) in the saturation region is presented by employing a relation between CNFET parameters meeting the experimental results. The methodology is based on the Stanford model and ballistic relation of one channel CNFET. In this regard, the ballistic relation is simplified to a closed-form I-V equation, and then, the parameters are estimated through the fitting algorithm by means of ICCAP and least square (LS) method, respectively, and the obtained equation is verified by the experimental results given in the literature. Additionally, an extended quantitative noise analysis is performed at the circuit level and the noise sources implemented in Verilog-A are added to the Stanford CNFET HSPICE model. Subsequently, with the accordance to the extracted I-V equation, a CNFET-based inductor-less broadband common-gate low noise amplifier (LNA) is designed theoretically and its results are confirmed in HSPICE based on the Stanford CNFET model, indicating a proper matching between analysis and simulation. The proposed CNFET-based LNA provides very high frequency bandwidth and also lower noise figure in comparison with its contemporary CMOS-based LNA, without any passive spiral inductor.Peer ReviewedPostprint (author's final draft

Design of Tunable Low-Noise Amplifier in 0.13um CMOS Technology for Multistandard RF Transceivers

The global market of mobile and wireless communications is witnessing explosive growth in size as well as radical changes. Third generation (3G) wireless systems have recently been deployed and some are still in the process. 3G wireless systems promise integration of voice and data communications with higher data rates and a superior quality of service compared to second generation systems. Unfortunately, more and more communication standards continue to be developed which ultimately requires specific RF/MW and baseband communication integrated circuits that are designed for functionality and compatibility with a specific type of network. Although communication devices such as cellular phones integrate different services such as voice, Bluetooth, GPS, and WLAN, each service requires its own dedicated radio transceiver which results in high power consumption and larger PCB area usage. With the rapid advances in silicon CMOS integrated circuit technology combined with extensive research, a global solutionswhich aims at introducing a global communication system that encompasses all communication standards appears to be emerging. State of the art CMOS technology not only has the capability of operation in the GHz range, but it also provides the advantage of low cost and high level of integration. These features propel CMOS technology as the ideal candidate for current trends, which currently aim to integrate more RF/MW circuits on the same chip. Armed with such technology ideas such as software radio look more attainable than they ever were in the past. Unfortunately, realizing true software radio for mobile applications still remains a tremendous challenge since it requires a high sampling rate and a wide-bandwidth Analog-to-Digital converter which is extremely power hungry and not suitable for battery operated mobile devices. Another approach to realize a flexible and reconfigurable RF/MW transceiver that could operate in a diverse mobile environment and provides a multiband and multistandard solution. The work presented in this thesis focuses on the design of an integrated and tunable low-noise amplifier as part of software defined radio (SDR)

Cmos Rf Cituits Sic] Variability And Reliability Resilient Design, Modeling, And Simulation

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos