End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Master'sMASTER OF ENGINEERIN

Fundamental Studies of Tin Whiskering in Microelectronics Finishes

Fundamental Studies of Tin Whiskering in Microelectronics Finishes Abstract Common electronics materials, such as tin, copper, steel, and brass, are ambient reactive under common use conditions, and as such are prone to corrosion. During the early 1940s, reports of failures due to electrical shorting of components caused by `whisker' (i.e., filamentary surface protrusion) growth on many surface types - including the aforementioned metals - began to emerge. Lead alloying of tin (3-10% by weight, typically in the eutectic proportion) eliminated whiskering risk for decades, until the July 2006 adoption of the Restriction of Hazardous Substances (RoHS) directive was issued by the European Union. This directive, which has since been adopted by California and parts of China, severely restricted the use of lead (<1000 ppm) in all electrical and electronics equipment being placed on the EU market, imposing the need for developing reliable new "lead-free" alternatives to SnPb. In spite of the abundance of modern-day anecdotes chronicling whisker-related failures in satellites, nuclear power stations, missiles, pacemakers, and spacecraft navigation equipment, pure tin finishes are still increasingly being employed today, and the root cause(s) of tin whiskering remains elusive. This work describes a series of structured experiments exploring the fundamental relationships between the incidence of tin whiskering (as dependent variable) and numerous independent variables. These variables included deposition method (electroplating, electroless plating, template-based electrochemical synthesis, and various physical vapor deposition techniques, including resistive evaporation, electron beam evaporation, and sputtering), the inclusion of microparticles and organic contamination, the effects of sample geometry, and nanostructuring. Key findings pertain to correlations between sample geometry and whisker propensity, and also to the stress evolution across a series of 4"-diameter silicon wafers of varying thicknesses with respect to the degree of post-metallization whiskering. Regarding sample geometry, it was found that smaller, thinner substrates displayed a more rapid onset of whiskering immediately following metallization. Changes in wafer-level stress were not found to correlate with whiskering morphology (number, density, length) after 6 weeks of aging. This result points either to the irrelevance of macrostress in the substrate/film composite, or to a difference in whiskering mechanism for rigid substrates (whose stress gradient over time is significant) when compared with thinner, flexible susbtrates (whose stress is less variable with time). Organic contamination was found to have no appreciable effect when explicitly introduced. Furthermore, electron-beam evaporated films whiskered more readily than films deposited via electroplating from baths containing organic "brighteners." Beyond such findings, novel in themselves, our work is also unique in that we emphasize the "clean" deposition of tin (with chromium adhesion layers and copper underlayers) by vacuum-based physical vapor deposition, to circumvent the question of contamination entirely. By employing silicon substrates exclusively, we have distinguished ourselves from other works (which, for example, use copper coupons fabricated from rolled shim stock) because we have better sample-to-sample consistency in terms of material properties, machinability, and orientation

Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry

Three-dimensional integration is a solution that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer warpage during the fabrication processes. Wafer warpage can cause chip misalignment and impose additional deformation. In an effort to investigate the TSV geometric effect, a large number of finite element analysis (FEA) simulations were performed to quantify the thermal stress distribution and the thermally induced curvature. It was found that the tapered geometry alone can induce significant wafer bending, which has not been reported by other researchers. The effect of taper angle, TSV radius, TSV pitch, and wafer thickness were quantitatively studied. In addition, the incorporations of anisotropic silicon property and intermediate layers between the copper TSV and silicon into the numerical models were assessed. Thermally induced stress concentration around copper TSV near the wafer surface can lead to degradation of the device performance by affecting the carrier mobility in transistors. This piezoresistivity effect can cause serious reliability concerns. The size of keep-out zone (KOZ), which is identified as a threshold of 5% carrier mobility change, was also quantified for various transistor types in different channel directions

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH

Comparing the Performance of Different Machine Learning Models in the Evaluation of Solder Joint Fatigue Life Under Thermal Cycling

Predicting the reliability of board-level solder joints is a challenging process for the designer because the fatigue life of solder is influenced by a large variety of design parameters and many nonlinear, coupled phenomena. Machine learning has shown promise as a way of predicting the fatigue life of board-level solder joints. In the present work, the performance of various machine learning models to predict the fatigue life of board-level solder joints is discussed. Experimental data from many different solder joint thermal fatigue tests are used to train the different machine learning models. A web-based database for storing, sharing, and uploading data related to the performance of electronics materials, the Electronics Packaging Materials Database (EPMD), has been developed and used to store and serve the training data for the present work. Data regression is performed using artificial neural networks, random forests, gradient boosting, extreme gradient boosting (XGBoost), and adaptive boosting with neural networks (AdaBoost). While previous works have studied artificial neural networks as a way to predict the fatigue life of board-level solder joints, the results in this paper suggest that machine learning techniques based on regression trees may also be useful in predicting the fatigue life of board-level solder joints. This paper also demonstrates the need for a large collection of curated data related to board-level solder joint reliability, and presents the Electronics Packaging Materials Database to meet that need

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Reliability assessment of telecommunications equipment

This thesis studies the reliability of telecommunications equipment, its components, and the systems made using those components. Special attention is paid to creating stronger links between the reliability analyses performed at different hierarchy levels. The thesis starts with a temperature derating study. It is found out that the generic handbook based procedures may not always be very attractive, as they do not take satisfactorily into account the actual lifetime requirements. An alternative approach is proposed as a remedy to the current situation. Thermal cycling requirement handbooks are surveyed, and based on the findings some enhancements are proposed. Next, a component and product specific approach to create thermal cycling requirements is suggested. When applying the new approach several factors can be taken into account: the product's lifetime requirement, the field environment, the reliability test result, and the statistical distribution of the component population. A new method of how to predict the reliability of a component population that is addressed to several, different field environments is presented. Ceramic, leadless components are studied by testing and by utilizing Engelmaier's analytical solder fatigue model and Finite Element (FE) simulations. A new approach to interpret the solder joint height in conjunction with solder castellations is introduced. Based on this, a very good correlation between the test results and the predictions based on Engelmaier's model can be obtained. The parameter sensitivity of both the Engelmaier's model and the FE analysis are studied and compared. Error margins based on the parameter sensitivity studies are given. Time-averaged hazard rate functions are studied in order to be able to use component level test data in simplistic parts-count method type reliability predictions. Finally, the availability of a full 3rd generation telecommunications network is studied.reviewe

Dynamic Mechanical and Failure Properties of Solder Joints

Ph.DDOCTOR OF PHILOSOPH