Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

In this paper we illustrate how by using advanced atomistic TCAD tools the interplay between long-range process variation and short-range statistical variability in FinFETs can be accurately modelled and simulated for the purposes of Design-Technology Co-Optimization (DTCO). The proposed statistical simulation and compact modelling methodology is demonstrated via a comprehensive evaluation of the impact of FinFET variability on SRAM cell stability

Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects

A new technique developed for the analysis of intrinsic sources of variability affecting the performance of semiconductor devices is presented. It is based on the creation of a fluctuation sensitivity map (FSM), which supplies spatial information about the source of variability affecting the device performance and reliability, providing useful advice in the development of fluctuation-resistant device architectures. We have applied the FSM to metal grain work-function variations (MGWVs), since they are one of the major contributors to device variability. This technique is computationally very efficient because, once the original FSM is created, it can be used to predict the MGWV for different metal gates or grain sizes (GSs). Two state-of-the-art devices were used as test-models: a 10.7-nm gate length Si FinFET and 10.4-nm gate length In0.53Ga0.47As FinFET. The cross-sectional shape (triangular, rectangular, or bullet), the metal used in the gate (TiN or WN), and the GS (10, 7, and 5 nm) have been used as test scenarios for this technique

Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on I – V characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The ION/IOFF ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger σVT than that from the LER and the RDs, respectively. However, the variability induced threshold voltage ( VT ) shift is minimal for the MGG (around 2 mV), but VT shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in VT and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies

Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability. The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows: Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle. Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved. Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope

Skybridge-3D-CMOS: A Fine-Grained Vertical 3D-CMOS Technology Paving New Direction for 3D IC

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is a fine-grained 3D IC fabric that uses vertically-stacked gates and 3D interconnections composed on vertical nanowires to yield orders of magnitude benefits over 2D ICs. This 3D fabric fully uses the vertical dimension instead of relying on a multi-layered 2D mindset. Its core fabric aspects including device, circuit-style, interconnect and heat-extraction components are co-architected considering the major challenges in 3D IC technology. In S3DC, the 3D interconnections provide greater routing capacity in both vertical and horizontal directions compared to conventional 3D ICs, which eliminates the routability issue in conventional 3D IC technology while enabling ultra-high density design and significant benefits over 2D. Also, the improved vertical routing capacity in S3DC is beneficial for achieving robust and high-density power delivery network (PDN) design while conventional 3D IC has design issues in PDN design due to limited routing resource in vertical direction. Additionally, the 3D gate-all-around transistor incorporating with 3D interconnect in S3DC enables significant SRAM design benefits and good tolerance of process variation compared to conventional 3D IC technology as well as 2D CMOS. The transistor-level (TR-L) monolithic 3D IC (M3D) is the state-of-the-art monolithic 3D technology which shows better benefits than other M3D approaches as well as the TSV-based 3D IC approach. The S3DC is evaluated in large-scale benchmark circuits with comparison to TR-L M3D as well as 2D CMOS. Skybridge yields up to 3x lower power against 2D with no routing congestion in benchmark circuits while TR-L M3D only has up-to 22% power saving with severe routing congestions in the design. The PDN design in S3DC show