Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact

This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge.Peer ReviewedPostprint (published version

Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact

This work was supported by the Spanish under Grant MCIN/AEI/10.13039/501100011033 and Project PID2019-103869RB-C33.This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge. KeywordsMCIN/AEI/10.13039/501100011033 PID2019-103869RB-C3

Nano-scale TG-FinFET: Simulation and Analysis

Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics

A novel optimization framework for controlling stabilization issue in design principle of FinFET based SRAM

The conventional design principle of the finFET offers various constraints that act as an impediment towards improving ther performance of finFET SRAM. After reviewing existing approaches, it has been found that there are not enough work found to be emphasizing on cost-effective optimization by addressing the stability problems in finFET design.Therefore, the proposed system introduces a novel optimization mechanism considering some essential design attributes e.g. area, thickness of fin, and number of components. The contribution of the proposed technique is to determine the better form of thickness of fin and its related aspect that can act as a solution to minimize various other asscoiated problems in finFET SRAM. Implemented using soft-computational approach, the proposed system exhibits that it offers better energy retention, lower delay, and potential capability to offer higher throughput irrespective of presence of uncertain amount of noise within the component

Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories

The continuous increase in transistor density based on Moore\u27s Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time

Expanded Noise Margin 10T SRAM Cell using Finfet Device

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential

Bandgap Reference Design at the 14-Nanometer FinFET Node

As supply voltages continue to decrease, it becomes harder to ensure that the voltage drop across a diode-connected BJT is sufficient to conduct current without sacrificing die area. One such solution to this potential problem is the diode-connected MOSFET operating in weak inversion. In addition to conducting appreciable current at voltages significantly lower than the power supply, the diode-connected MOSFET reduces the total area for the bandgap implementation. Reference voltage variations across Monte Carlo perturbations are more pronounced as the variation of process parameters are exponentially affected in subthreshold conduction. In order for this proposed solution to be feasible, a design methodology was introduced to mitigate the effects of process variation. A 14 nm bandgap reference was created and simulated across Monte Carlo perturbations for 100 runs at nominal supply voltage and 10% variation of the power supply in either direction. The best case reference voltage was found and used to verify the proposed resistive network solution. The average temperature coefficient was measured to be 66.46 ppm/◦C and the voltage adjustment range was found to be 204.1 mV. The two FinFET subthreshold diodes consume approximately 2.8% of the area of the BJT diode equivalent. Utilizing an appropriate process control technique, subthreshold bandgap references have the potential to overtake traditional BJT-based bandgap architectures in low-power, limited-area applications

An Enhanced Statistical Phonon Transport Model for Nanoscale Thermal Transport and Design

Managing thermal energy generation and transfer within the nanoscale devices (transistors) of modern microelectronics is important as it limits speed, carrier mobility, and affects reliability. Application of Fourier’s Law of Heat Conduction to the small length and times scales associated with transistor geometries and switching frequencies doesn’t give accurate results due to the breakdown of the continuum assumption and the assumption of local thermodynamic equilibrium. Heat conduction at these length and time scales occurs via phonon transport, including both classical and quantum effects. Traditional methods for phonon transport modeling are lacking in the combination of computational efficiency, physical accuracy, and flexibility. The Statistical Phonon Transport Model (SPTM) is an engineering design tool for predicting non-equilibrium phonon transport. The goal of this work has been to enhance the models and computational algorithms of the SPTM to elevate it to have a high combination of accuracy and flexibility. Four physical models of the SPTM were enhanced. The lattice dynamics calculation of phonon dispersion relations was extended to use first and second nearest neighbor interactions, based on published interatomic force constants computed with first principles Density Functional Theory (DFT). The computation of three phonon scattering partners (that explicitly conserve energy and momentum) with the inclusion of the three optical phonon branches was applied using scattering rates computed from Fermi’s Golden Rule. The prediction of phonon drift was extended to three dimensions within the framework of the previously established methods of the SPTM. Joule heating as a result of electron-phonon scattering in nanoscale electronic devices was represented using a modal specific phonon source that can be varied in space and time. Results indicate the use of first and second nearest neighbor lattice dynamics better predicted dispersion when compared to experimental results and resulted in a higher fidelity representation of phonon group velocities and three phonon scattering partners in an anisotropic manner. Three phonon scattering improvements resulted in enhanced fidelity in the prediction of phonon modal decay rates across the wavevector space and thus better representation of non-equilibrium behavior. Comparisons to the range of phonon transport modeling approaches from literature verify that the SPTM has higher phonon fidelity than Boltzmann Transport Equation and Monte Carlo and higher length scale and time scale fidelity than Direct Atomic Simulation. Additional application of the SPTM to both a 1-d silicon nanowire transistor and a 3-d FinFET array transistor in a transient manner illustrate the design capabilities. Thus, the SPTM has been elevated to fill the gap between lower phonon fidelity Monte Carol (MC) models and high fidelity, inflexible direct quantum simulations (or Direct Atomic Simulations (DAS)) within the field of phonon transport modeling for nanoscale electronic devices. The SPTM has produced high fidelity device level non-equilibrium phonon information in a 3-d, transient manner where Joule heating occurs. This information is required due to the fact that effective lattice temperatures are not adequate to describe the local thermal conditions. Knowledge of local phonon distributions, which can’t be determined from application of Fourier’s law, is important because of effects on electron mobility, device speed, leakage, and reliability

Cross-layer system reliability assessment framework for hardware faults

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.Peer ReviewedPostprint (author's final draft