Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques

A higher performance of computing systems is being demanded year after year, driving the digital industry to fiercely compete for offering the fastest computer system at the lowest cost. In addition, as computing system performance is growing, power delivery networks (PDN) and power integrity (PI) designs are getting increasingly more relevance due to the faster speeds and more parallelism required to obtain the required performance growth. The largest data throughput at the lowest power consumption is a common goal for most of the commercial computing systems. As a consequence of this performance growth and power delivery tradeoffs, the complexity involved in analyzing and designing PDN in digital systems is being increased. This complexity drives longer design cycle times when using traditional design tools. For this reason, the need of using more efficient design methods is getting more relevance in order to keep designing and launching products in a faster manner to the market. This trend pushes PDN designers to look for methodologies to simplify analysis and reduce design cycle times. The main objective for this Master’s thesis is to propose alternative methods by exploiting reliable simulation approaches and efficient numerical optimization techniques to analyze and design PDN to ensure power integrity. This thesis explores the use of circuital models and electromagnetic (EM) field solvers in combination with numerical optimization methods, including parameter extraction (PE) formulations. It also establishes a sound basis for using space mapping (SM) methodologies in future developments, in a way that we exploit the advantages of the most accurate and powerful models, such as 3D full-wave EM simulators, but conserving the simplicity and low computational resourcing of the analytical, circuital, and empirical models

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

3D modeling and integration of current and future interconnect technologies

Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit performance and signal integrity in the circuit design phase. A full phase simulation for performance estimation of a large-scale circuit not only require a massive computational resource but also need a lot of time to produce acceptable results. The estimation of performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect capacitance. So, an accurate model for interconnect capacitance can be used in the circuit CAD (computer-aided design) tools for circuit performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the interconnect lines. Closed-form equations have been derived analytically for ground and coupling capacitance. First, the capacitance model for a single line is developed, and then the new model is used to derive expressions for the capacitance of a line surrounded by neighboring lines in the same and the adjacent layers above and below. These expressions are simple, and the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias. Signal speed in current digital systems depends mainly on the delay of interconnects. To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit (vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to ensure much smaller interconnect lengths, and lower delay and power consumption compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit performance depends on different electrical parameters (capacitance, resistance, inductance) of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance, resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived from the physical shape and the size of the TSV. The modeling approach is comprehensive and includes both the cylindrical and tapered TSVs as well as the bumps. On-chip integration of inductors has always been very challenging. However, for sub- 14nm on-chip applications, large area overhead imposed by the on-chip capacitors and inductors has become a more severe concern. To overcome this issue and ensure power integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The proposed TSV based inductor has the potential to achieve both high density and high performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV based inductor is also presented. The implementation of the VCO is intended to study the feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor

Signal and power integrity co-simulation using the multi-layer finite difference method

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.Ph.D.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitarama

Design of Low-Cost Energy Harvesting and Delivery Systems for Self-Powered Devices: Application to Authentication IC

This thesis investigates the development of low-cost energy harvesting and delivery systems for low-power low-duty-cycle devices. Initially, we begin by designing a power management scheme for on-demand power delivery. The baseline implementation is also used to identify critical challenges for low-power energy harvesting. We further propose a robust self-powered energy harvesting and delivery system (EHDS) design as a solution to achieve energy autonomy in standalone systems. The design demonstrates a complete ecosystem for low-overhead pulse-frequency modulated (PFM) harvesting while reducing harvesting window confinement and overall implementation footprint. Two transient-based models are developed for improved accuracy during design space exploration and optimization for both PFM power conversion and energy harvesting. Finally, a low-power authentication IC is demonstrated and projected designs for self-powered System-on-Chips (SoCs) are presented. The proposed designs are proto-typed in two test-chips in a 65nm CMOS process and measurement data showcase improved performance in terms of battery power, cold-start duration, passives (inductance and capacitance) needed, and end-to-end harvesting/conversion efficiency.Ph.D

Energy management techniques for ultra-small bio-medical implants

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 167-174).Trends in the medical industry have created a growing demand for implantable medical devices. In particular, the need to provide medical professionals a means to continuously monitor bio-markers over long time scales with increased precision is paramount to efficient healthcare. To make medical implants more attractive, there is a need to reduce their size and power consumption. Small medical implants would allow for less invasive procedures and greater comfort for patients. The two primary limitations to the size of small medical implants are the batteries that provide energy to circuit and sensor components, and the antennas that enable wireless communication to terminals outside of the body. In this work we present energy management and low-power techniques to help solve the engineering challenges posed by using ultracapacitors for energy storage. A major problem with using any capacitor as an energy source is the fact that its voltage drops rapidly with decreasing charge. This leaves the circuit to cope with a large supply variation and can lead to energy being left on the capacitor when its voltage gets too low to supply a sufficient supply voltage for operation. Rather than use a single ultracapacitor, we demonstrate higher energy utilization by splitting a single capacitor into an array of capacitors that are progressively reconfigured as energy is drawn out. An energy management IC fabricated in 180-nm CMOS implements a stacking procedure that allows for more than 98% of the initial energy stored in the ultracapacitors to be removed before the output voltage drops unsuitably low for circuit operation. The second part of this work develops techniques for wide-input-range energy management. The first chip implementing stacking suffered an efficiency penalty by using a switchedcapacitor voltage regulator with only a single conversion ratio. In a second implementation, we introduce a better solution that preserves efficiency performance by using a multiple conversion ratio switched-capacitor voltage regulator. At any given input voltage from an ultracapcitor array, the switched-capacitor voltage regulator is configured to maximize efficiency. Fabricated in a 180-nm CMOS process, the chip achieves a peak efficiency of 90% and the efficiency does not fall below 70% for input voltages between 1.25 and 3 V.by William R. Sanchez.Ph.D

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Optimal Power Delivery Strategy in Modern VLSI Design

Department of Electrical EngineeringIn a modern very-large-scale integration (VLSI) designs, heterogeneous architectural structures and various three-dimensional (3D) integration methods have been used in a hybrid manner. Recently, the industry has combined 3D VLSI technology with the heterogeneous technology of modern VLSI called chiplet. The 3D heterogeneous architectural structure is growing attention because it reduces costs and time-to-market by increasing manufacturing yield with high integration rate and modularization. However, a main design concern of heterogeneous 3D architectural structure is power management for lowering power consumption with maintaining the required power integrity from IR drop. Although the low-power design can be realized in front-end-of-line level by reduced power supply complementary metal???oxide???semiconductor technologies, the overall low-power system performance is available with a proper design of power delivery network (PDN) for chip-level modules and system-level architectural structure. Thus, there is a demand for both the coanalysis and optimization for both chip-level and system-level. We analyzed and optimized power delivery on-chip in various 3D integration environments, and we also have proposed a chip-package-PCB coanalysis methodology at the system level. For through-silicon-via (TSV)-based 3D integration circuit (IC), We have investigated and analyzed the voltage noise in a multi-layer 3D stacking with partial element equivalent circuit (PEEC)-based on-chip PDN and frequency-dependent TSV models. We also have proposed a wire-added multi-paired on-chip PDN structure to reduce voltage noise to reduce IR drop. The performance of TSV-based 3D ICs has also been improved by reducing wake-up time through our proposed adaptive power gating strategy with tapered TSVs. For die-to-wafer 3D IC, we have proposed a power delivery pathfinding methodology, which seeks to identify a nearly optimal PDN for a given design and PDN specification. Our pathfinding methodology exploits models for routability and worst IR drop, which helps reducing iterations between PDN design and circuit design in 3D IC implementation. We also have extended the observation to system-level, we have proposed a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our coanalysis methodology can analyze the tendencies in power integrity by using parametric methods with consideration of package-on-package integration. We have proved that our methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of high-speed low-power memory interfaces. Finally, we have proposed analysis and optimization methodologies that are generally applicable to various integration methods used in modern VLSI designs as computer-aided-design-based solutions.clos

D-Band downconversion mixer design in CMOS-SOI

Abstract. The current surge in research interest around the sub-THz frequency region comes as a no surprise. The potential for greater data rates and available bandwidths are just a couple reasons why research around these frequencies should be prioritized. Many viable receiver structures have been presented for these frequency regions, but they all have one thing in common: They all include a downconversion mixer. The mixer is a crucial piece in the receiver structure, converting the higher frequency radio frequency (RF) signal to a much lower intermediate frequency (IF) signal using multiplication with a local oscillator (LO) signal. The resulting waveform is much easier to handle for signal processing that comes after. The downconversion should be able to provide a fair amount of gain to the converted signal on a wide range of input signals, measured with the 1dB compression point. The noise figure is also a major consideration for RF-devices, but in the case of the mixer, its importance is not as prevalent as it is for the LNA that precedes it, since the noise of the mixer is attenuated by the gain of the previous stages. This master’s thesis work introduces the basic theory around downconversion mixers, followed by the design of a mixer from schematic level circuit design all the way to the physical layout. The physical design is done using 22nm FDSOI technology, provided by GlobalFoundries. The design is made for a direct conversion receiver using Gilbert cell topology, meaning image rejection is reasonable and depends only on the received signal itself, and good noise and feedthrough performance should be expected in simulations. The mixer is to downconvert a 151 GHz signal down to 0–1 GHz, using an LO signal between 150–151 GHz. Two iterations of the mixer are shown in the end results, the first one being based on the schematic design, and the second one with adjustments made for better performance. While driving a high impedance 500 Ohm load, the second iteration was able to reach a conversion gain of -10.0 dB with a 1dB compression point of 6.4 dBm while dissipating 4.7 mW of power. DSB noise figure was simulated to be 17.3 dB and the LO leakage to the IF output at -27.7 dBm.Alaspäin taajuusmuuntavan sekoittimen suunnittelu D-kaistalle käyttäen CMOS-SOI teknologiaa. Tiivistelmä. Nykyinen tutkimuksen keskittyminen millimetriaalto ja THz taajuusalueille ei tule kenellekään yllätyksenä. Suurempien datanopeuksien ja vapaiden taajuuskaistojen potentiaali ovat vain joitain monista hyvistä käytännön syistä, miksi tutkimusta näiden taajuuksien ympärillä priorisoidaan. Monia käytännöllisiä vastaanotinrakenteita on esitetty näille taajuusalueille ja niillä on kaikilla yksi yhteinen tekijä: tajuusmuunnin alemmille taajuuksille. Taajuusmuunnin eli sekoitin on olennainen osa vastaanotinrakenteita, muuntaen korkeamman radiotaajuuden (RF) matalammalle välitaajuudelle (IF) käyttäen taajuuksien sekoittamista paikallisoskillaattorilla (LO). Mikserin ulostulosignaali on signaalinprosessoinnin näkökulmasta paljon käytännöllisempi. Alaspäin taajuusmuuntavan mikserin tulee pystyä vahvistamaan laajaa skaalaa erivahvuisia signaaleja, minkä ylärajaa mittaamme 1 dB kompressiopisteellä. Radiolaitteistossa kohinaluku tulee yleensä myös ottaa huomioon, mutta johtuen mikserin sijainnista vastaanotinketjussa, kohinaluku vaimenee suhteessa sitä edeltävien vahvistuksien verran, eikä siksi ole niin kriittinen. Tämä diplomityö esittelee lukijalle ensiksi alaspäin muuntavan taajuussekoittimen perusteorian, toisena sen teoreettisen piirikaavion suunnittelun sekä sen simuloinnin tuloksia, ja viimeisenä fyysisen layoutin suunnittelun sekä sen simuloinnin tulokset. Fyysisen layoutin suunnittelu ja simulointi tehdään käyttäen GlobalFoundries 22nm FDSOI teknologiaa. Suunnittelu tehdään suoramuunnosvastaanottimelle käyttäen Gilbertin solu topologiaa, eliminoiden peilitaajuuksista aiheutuvat ongelmat, sekä vähentäen kohinan sekä ei-haluttujen signaalien läpivuotojen vaikutusta. Sekoittimen tulee muuntaa 151 GHz signaali n. 0–1 GHz kantataajuudelle käyttäen LO-signaalia taajuusvälillä 150–151 GHz. Lopullisissa tuloksissa vertaillaan kahta eri iteraatiota. Ensimmäisenä versiota, joka luotiin alun perin teoriapohjaisen piirisuunnittelun pohjalta, sekä toista versiota, missä useilla parannuksilla mikserin suorituskykyä saatiin parannettua. Korkeaimpedanssista 500 Ohmin kuormaa ajaessa mikseri ylsi -10.0 dB vahvistukseen, 1 dB kompressiopiste oli 6.4 dB kuluttaen 4.7 mW virtaa käytössä. Kohinaluvuksi simuloitiin 17.3 dB, sekä LO signaalin vuodosta IF lähtöön oli -27.7 dBm