35 research outputs found
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications
Bandpass sigma-delta modulators combine oversampling and noise shaping to get
very high resolution in a limited bandwidth. They are widely used in applications that
require narrowband high-resolution conversion at high frequencies. In recent years interests
have been seen in wireless system and software radio using sigma-delta modulators to
digitize signals near the front end of radio receivers. Such applications necessitate clocking
the modulators at a high frequency (MHz or above). Therefore a loop filter is required in
continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime
circuits (e.g., using switched capacitors) where the maximum clocking rate is limited
by the bandwidth of Opamp, switchĂs speed and settling-time of the circuitry.
In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking
at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new
calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the
modulator. The continuous-time loop filter is based on Gm-C resonators. A novel
transconductance amplifier has been developed with high linearity at high frequency. Qfactor
of filter is enhanced by tunable negative impedance which cancels the finite output
impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal
standard analog CMOS technology. Postlayout simulation in CADENCE
demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1
MHz bandwidth. The modulatorĂs power consumption is 302 mW from supply power of ñ
1.65V
Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters
In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based
Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS