1,356 research outputs found

    Leakage current and breakdown of HfO2/InGaAs MOS capacitors

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    With the constant downscaling of transistors, silicon as a production material is falling out of favour because of increasing power consumption when the size of devices becomes smaller. Compound materials from group III-V in the table of elements are promising candidates to replace silicon. The aim of this work was to study current-voltage characteristics of a MOS capacitor made of the III-V compound InGaAs. Three samples were produced using atomic layer deposition (ALD) to apply an oxide layer of the high-Îș material HfO2 on the InGaAs surface. The thicknesses of these oxide layers were 4 nm, 6 nm and 6 nm where one of the 6 nm samples underwent post-metallisation annealing (PMA). The electric field required to cause a hard breakdown through the oxide was found to be ~0.81 GV/m for the 6 nm annealed sample, ~0.90 GV/m for the 6 nm as deposited sample and ~1.13 GV/m for the 4 nm sample. In all three samples, the breakdown field was widely distributed which indicates an InGaAs-HfO2 interface with a large variation in density of interface traps across the layer. The breakdown field was found to decrease with oxide thickness and PMA treatment, which might be attributed to a percolation path through the oxide being created more easily due to higher polycrystallinity in the thicker oxides. The dominant leakage mechanism at higher biases was determined to be Fowler-Nordheim tunneling and was assumed to be direct tunneling or trap assisted tunneling at low bias. Temperature dependency measurements suggested that trap assisted tunneling gained significance at low bias when the temperature increased.Antalet mĂ€nniskor i vĂ€rlden med tillgĂ„ng till elektroniska produkter som datorer och smartphones ökar kraftigt. I takt med att antalet produkter gĂ„r upp sĂ„ ökar Ă€ven deras prestanda. Men Ă€r det bara att fortsĂ€tta bygga mindre och bĂ€ttre komponenter för alltid? I den hĂ€r artikeln beskrivs ett bekymmer som uppstĂ„r dĂ„ elektroniska komponenter blir mindre, och nĂ„gra resultat frĂ„n ett arbete som utförts i ett försök att hitta lösningar till problemet. Datorer, smartphones och liknande moderna elektroniska produkter har en sak gemensamt: de skulle inte existera om det inte vore för transistorer. De komponenter som bygger upp alla tekniska prylar innehĂ„ller mĂ„nga miljoner, eller till och med miljarder, transistorer. Transistorns funktion kan liknas lite med en dörr. NĂ€r ström gĂ„r igenom en komponent i datorn sĂ„ tar den olika vĂ€gar beroende om dörrarna den passerar Ă€r öppna eller stĂ€ngda. UtifrĂ„n den vĂ€g genom labyrinten av dörrar som strömmen tar sĂ„ tolkar datorn hĂ€ndelsen pĂ„ olika sĂ€tt. Den vanligaste typen av transistor Ă€r en MOSFET (Metal Oxide Semiconductor Field Effect Transistor) som bestĂ„r av tre lager av en metall, en oxid och en halvledare. Genom historien har kisel varit det absolut dominanta halvledarmaterialet och kiseldioxid har anvĂ€nts som oxidlager. Men nĂ€r teknologin gĂ„r framĂ„t sĂ„ gĂ„r storleken pĂ„ elektroniska produkter och transistorer nedĂ„t, och dĂ„ uppstĂ„r ett problem med kiseltransistorer. NĂ€r transistorn Ă€r vĂ€ldigt liten sĂ„ börjar det lĂ€cka ström igenom oxidlagret. Denna lĂ€ckta ström gĂ„r förlorad, vilket innebĂ€r att energikonsumtionen gĂ„r upp. För att lösa problemet med ökad energikonsumtion sĂ„ kan andra Ă€mnen Ă€n kisel anvĂ€ndas vid tillverkningen av transistorerna. Indiumgalliumarsenid som halvledare och hafniumdioxid som oxidlager Ă€r en lovande kombination av Ă€mnen. Med hafniumdioxid istĂ€llet för kiseldioxid kan transistorn tillverkas pĂ„ ett sĂ€tt sĂ„ att lĂ€ckströmmen blir mycket mindre, trots att storleken pĂ„ transistorn minskar, för att undvika en ökning av energikonsumtionen. Indiumgalliumarsenid har ocksĂ„ sina fördelar över kisel som halvledarmaterial. I indiumgalliumarsenid kan strömmen röra sig snabbare Ă€n i kisel, vilket gör att processer i datorn kan ske kvickare. Det kan ses som att dörrarna öppnas eller stĂ€ngs snabbare mellan varje kommando som datorn ska tolka. I indiumgalliumarsenid krĂ€vs det Ă€ven mindre energi för att öppna eller stĂ€nga en dörr, vilket ocksĂ„ leder till lĂ€gre energikonsumtion. I det hĂ€r arbetet undersöktes transistorer av indiumgalliumarsenid och hafniumdioxid för att jĂ€mföra hur olika tillverkningsprocesser pĂ„verkar deras egenskaper. Det mĂ€ttes bl.a. hur mycket lĂ€ckström det gĂ„r igenom hafniumdioxiden för olika tjocklekar av lagret. Det mĂ€ttes ocksĂ„ hur mycket transistorerna tĂ„l innan de gĂ„r sönder, vilket de gör om de utsĂ€tts för en för hög spĂ€nning. I tillverkningsprocessen finns det mĂ„nga andra parametrar Ă€n tjockleken som kan Ă€ndras om man vill jĂ€mföra olika metoder, och ofta sĂ„ glödgas transistorn efter tillverkning i ett försök att förbĂ€ttra dess egenskaper. Glödgning Ă€r en process dĂ€r transistorn behandlas i en ugn och vĂ€rms upp till en hög temperatur under en liten tid. Det visade sig att transistorerna med ett lite tunnare lager hafniumdioxid pĂ„ 4 nm var tĂ„ligare Ă€n de med 6 nm. Vid jĂ€mförelser av olika transistorer tillverkade i det hĂ€r arbetet sĂ„ visade det sig ocksĂ„ att resultaten försĂ€mrades hos transistorer som glödgats under tillverkningsprocessen. Bland alla fördelar med indiumgalliumarsenid och hafniumdioxid över motsvarande kiselĂ€mnen sĂ„ finns det förstĂ„s Ă€ven nackdelar. Kisel Ă€r otroligt lĂ€ttillgĂ€ngligt och billigt eftersom det utvinns ur sand, och transistorer av kisel Ă€r vĂ€ldigt lĂ€tta att tillverka. Detsamma kan inte sĂ€gas för indiumgalliumarsenid och hafniumdioxid dĂ€r Ă€mnena Ă€r dyra och processen att fĂ€sta oxidlagret pĂ„ halvledaren Ă€r mycket svĂ„rare att fĂ„ rĂ€tt Ă€n vad det Ă€r med kisel. Förhoppningarna Ă€r dock stora om att det inom en snar framtid ska finnas lösningar till hands som bĂ„de kan öka prestandan och minska energikonsumtionen hos elektroniska produkter utan en alltför stor ökning av kostnaden

    Silicon Nanowire FinFETs

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    Fabrication and Characterization of AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors for High Power Applications

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    AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach

    Electrical Characterisation of III-V Nanowire MOSFETs

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    The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

    Modeling the Interdependences between Voltage Fluctuation and BTI Aging

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    With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently, as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands

    Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

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    With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∌50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 ”A/”m) and Ion up to 40 ”A/”m at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∌0.01 ”m2 footprint, thus increasing both functional density andenergy efficiency

    Evaluation of 4h-Sic Photoconductive Switches for Pulsed Power Applications Based on Numerical Simulations

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    Since the early studies by Auston, photoconductive semiconductor switches (PCSSs) have been investigated intensively for many applications owing to their unique advantages over conventional gas and mechanical switches. These advantages include high speeds, fast rise times, optical isolation, compact geometry, and negligible jitter. Another important requirement is the ability to operate at high repetition rates with long device lifetimes (i.e., good reliability without degradation). Photoconductive semiconductor switches (PCSSs) are low-jitter compact alternatives to traditional gas switches in pulsed power systems. The physical properties of Silicon Carbide (SiC), such as a large bandgap (3.1-3.35 eV), high avalanche breakdown field (~3 MV/cm), and large thermal conductivity (4-5 W/cm-K) with superior radiation hardness and resistance to chemical attack, make SiC an attractive candidate for high voltage, high temperature, and high power device applications. A model-based analysis of the steady-state, current-voltage response of semi-insulating 4H-SiC was carried out to probe the internal mechanisms, focusing on electric field driven effects. Relevant physical processes, such as multiple defects, repulsive potential barriers to electron trapping, band-to-trap impact ionization, and field-dependent detrapping, were comprehensively included. Results of our model matched the available experimental data fairly well over orders of magnitude variation in the current density. A number of important parameters were also extracted in the process through comparisons with available data. Finally, based on our analysis, the possible presence of holes in the samples could be discounted up to applied fields as high as 275 kV/cm. In addition, calculations of electric field distributions in a SiC photoconductive semiconductor switch structure with metal contacts employing contact extensions on a high-k HfO2 dielectric were carried out, with the goal of assessing reductions in the peak electric fields. For completeness, analysis of thermal heating in a lateral PCSS structure with such modified geometries after photoexcitation was also included. The simulation results of the electric field distribution show that peak electric fields, and hence the potential for device failure, can be mitigated by these strategies. A combination of the two approaches was shown to produce up to a ~67% reduction in peak fields. The reduced values were well below the threshold for breakdown in SiC material using biasing close to experimental reports. The field mitigation was shown to depend on the length of the metal overhang. Further, the calculations show that, upon field mitigation, the internal temperature rise would also be controlled. A maximum value of 980 K was obtained here for an 8 ns electrical pulse at a 20 kV external bias, which is well below the limits for generating local stress or cracks or defects

    The Effects of Temperature and Electron Radiation on the Electrical Properties of AlGaN/GaN Heterostructure Field Effect Transistors

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    AlxGa1-xN/GaN Heterostructure Field Effect Transistors (HFETs) have come under increased study, in recent years, owing to their highly desirable material and electrical properties, ruggedness, and survivability even during and after exposure to extreme temperature and radiation environments. These devices or similar devices constructed of AlGaN and/or GaN materials are being researched for their potential applications in many military and space based systems. In this study, unpassivated and SiN passivated Al0.27Ga0.73N/GaN HFETs were subjected to electron radiation at incident energies of 0.5MeV and 1.0MeV and fluences from 5x1014 to 5x1015 [e-/cm2] while maintained in a 10-6 Torr or higher vacuum at liquid nitrogen temperature (LN). The primary focus of the research was the effects of electron radiation and temperature on drain current, gate leakage current, threshold voltage shift, and gate-channel capacitance. Measurements were taken of transistor current, gate-channel capacitance, and gate leakage current vs. gate bias at 4°K temperature intervals beginning at LN through room temperature (RT). The resulting gate leakage currents were fitted to a Trap-Assisted Tunneling model and transistor currents were compared to a Charge Control model to evaluate post-irradiation change mechanisms to the parameters of these models. Post-irradiation drain currents increased for all devices, with a consistently lesser increase observed for passivated devices. Most post-irradiation increases returned to nearly pre-irradiation levels after an RT anneal period. Threshold voltage shifts averaged -0.5V for unpassivated and -0.2V for passivated HFETs, showed negligible temperature dependence, and returned to near pre-irradiation values, after RT anneal periods. Gate leakage currents showed post-irradiation increases for all devices
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