Neuromorphic Computing with Deeply Scaled Ferroelectric FinFET in Presence of Process Variation, Device Aging and Flicker Noise

This paper reports a comprehensive study on the applicability of ultra-scaled ferroelectric FinFETs with 6 nm thick hafnium zirconium oxide layer for neuromorphic computing in the presence of process variation, flicker noise, and device aging. An intricate study has been conducted about the impact of such variations on the inference accuracy of pre-trained neural networks consisting of analog, quaternary (2-bit/cell) and binary synapse. A pre-trained neural network with 97.5% inference accuracy on the MNIST dataset has been adopted as the baseline. Process variation, flicker noise, and device aging characterization have been performed and a statistical model has been developed to capture all these effects during neural network simulation. Extrapolated retention above 10 years have been achieved for binary read-out procedure. We have demonstrated that the impact of (1) retention degradation due to the oxide thickness scaling, (2) process variation, and (3) flicker noise can be abated in ferroelectric FinFET based binary neural networks, which exhibits superior performance over quaternary and analog neural network, amidst all variations. The performance of a neural network is the result of coalesced performance of device, architecture and algorithm. This research corroborates the applicability of deeply scaled ferroelectric FinFETs for non-von Neumann computing with proper combination of architecture and algorithm

Phase-field Simulations of Polarization Variations in Polycrystalline Hf0.5Zr0.5O2 based MFIM: Voltage-Dependence and Dynamics

In this work, we investigate the device-to-device variations in remanent polarization of Hafnium-Zirconium-Oxide based Metal-Ferroelectric-Insulator-Metal (MFIM) stacks. We consider the effects of polycrystallinity in conjunction with multi-domain effects in HZO to understand the dependencies of variations on static and dynamic voltage stimuli using our 3D dynamic multi-grain phase-field simulation framework. We examine the trends in variations due to various design factors - set voltage, pulse amplitude and pulse width and correlate them to the dynamics of polarization switching and the underlying mechanisms. According to our analysis, variations exhibit a non-monotonic dependence on set voltage due to the interplay between voltage-dependent switching mechanisms and the polycrystalline structure. We further report that towards the higher end of the set voltages, collapsing of oppositely polarized domains can lead to increase in variations. We also show that ferroelectric thickness scaling lowers the device-to-device variations. In addition, considering the dynamics of polarization switching, we signify the key role of voltage and temporal dependence of domain nucleation in dictating the trends in variations. Finally, we show that to reach a target mean polarization, using a pulse with lower amplitude for longer duration results in lower variations compared to higher amplitude pulse for a shorter duration

FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors

Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature

Remote Surface Optical Phonon Scattering in Ferroelectric Ba0.6_{0.6}Sr0.4_{0.4}TiO3_{3} Gated Graphene

We report the effect of remote surface optical (RSO) phonon scattering on carrier mobility in monolayer graphene gated by ferroelectric oxide. We fabricate monolayer graphene transistors back-gated by epitaxial (001) Ba$_{0.6}$Sr$_{0.4}$TiO$_{3}$ films, with field effect mobility up to 23,000 cm$^{2}$V$^{-1}$s$^{-1}$ achieved. Switching the ferroelectric polarization induces nonvolatile modulation of resistance and quantum Hall effect in graphene at low temperatures. Ellipsometry spectroscopy studies reveal four pairs of optical phonon modes in Ba$_{0.6}$Sr$_{0.4}$TiO$_{3}$, from which we extract the RSO phonon frequencies. The temperature dependence of resistivity in graphene can be well accounted for by considering the scattering from the intrinsic longitudinal acoustic phonon and the RSO phonon, with the latter dominated by the mode at 35.8 meV. Our study reveals the room temperature mobility limit of ferroelectric-gated graphene transistors imposed by RSO phonon scattering.Comment: 15 pages, 6 figure

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, highspeed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Polarization-induced transport in ferroelelctric organic field-effect transistors

In this research we study the role of ferroelectric dielectrics in organic field-effect transistors (FETs) to understand the mechanism of charge transport in organic semiconductors. The ferroelectric nature of the polymer, poly(vinylidene fluoride) (PVDF)), has been known for over 45 years. However, its role in interfacial transport in organic/polymeric FETs is not that well understood. PVDF and its copolymer, polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE), as a dielectric in organic FETs is a perfect test-bed for conducting transport studies where a systematic tuning of the dielectric constant with temperature may be achieved. By choosing small molecule organic semiconductors -- pentacene and 6,13 bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) -- along with a copolymer PVDF-TrFE as the dielectric layer, the FET characteristics are monitored as a function of temperature. Pentacene FETs show a weak temperature dependence of the charge carrier mobility in the ferroelectric phase of PVDF-TrFE, which is attributed to polarization fluctuation driven transport resulting from a coupling of the charge carriers to the surface phonons of the dielectric layer. A negative coefficient of carrier mobility is observed in TIPS-pentacene upwards of 200 K with the ferroelectric dielectric, while an activated transport is observed with non-ferroelectric dielectrics. We show that this behavior is correlated with the nature of the trap states in TIPS-pentacene. We also developed the method of dipole engineering of the PVDF-TrFE films to enhance the properties of organic FETs. PVDF-TrFE, despite its applications in a vast range of work (including as a gate dielectric in organic FET and sensing applications) poses concerns such as higher conductivity compared to other polymer non-ferroelectric dielectrics. We have come up with new methods of electrical poling the dielectric layer to enhance FET performance as well as reduce gate leakage issues. We demonstrate the effect of polarization rotation in PVDF-TrFE on the performance of small-molecule-based organic FETs. The subthreshold swing and other transistor parameters in organic FETs can be controlled in a reversible fashion by switching the polarization direction in the PVDF-TrFE layer. We further demonstrate a novel method of selective poling of the dielectric layer. By using solution processed TIPS-pentacene as the organic semiconductor, it is shown that textured poling of the PVDF-TrFE layer dramatically improves FET properties compared to unpoled or uniformly poled ferroelectric films. The texturing is achieved by first vertically poling the PVDF-TrFE film and then laterally poling the dielectric layer close to the gate electrode. TIPS-pentacene FETs show on/off ratios of 105 and hole mobilities of 1 cm2/Vs under ambient conditions with operating voltages well below-4 V. This research opens prospects of achieving low-operating FETs without any expensive patterning techniques.Includes bibliographical reference

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Fundamental design principles of novel MEMS based Landau switches, sensors, and actuators : Role of electrode geometry and operation regime

Microelectromechanical systems (MEMS) are considered as potential candidates for More-Moore and More-than-Moore applications due to their versatile use as sensors, switches, and actuators. Examples include accelerometers for sensing, RF-MEMS capacitive switches in communication, suspended-gate (SG) FETs in computation, and deformable mirrors in optics. In spite of the wide range of applications of MEMS in diverse fields, one of the major challenges for MEMS is their instability. Instability divides the operation into stable and unstable regimes and poses fundamental challenges for several applications. For example: Tuning range of deformable mirrors is fundamentally limited by pull-in instability, RF-MEMS capacitive switches suffer from the problem of hard landing, and intrinsic hysteresis of SG-FETs puts a lower bound on the minimum power dissipation. ^ In this thesis, we provide solutions to the application specific problems of MEMS and utilize operation in or close to unstable regime for performance enhancement in several novel applications. Specifically, we propose the following: (i) novel device concepts with nanostructured electrodes to address the aforementioned problems of instability, (ii) a switch with hysteresis-free ideal switching characteristics based on the operation in unstable regime, and (iii) a Flexure biosensor that operates at the boundary of the stable and unstable regimes to achieve improved sensitivity and signal-to-noise ratio. In general, we have advocated electrode geometry as a design variable for MEMS, and used MEMS as an illustrative example of Landau systems to advocate operation regime as a new design variabl