Power supply noise reduction in 90 nm using active decap

On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors [4]. They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decap’s area, a new active decap design is proposed for 90 nm technology

A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology

An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB power gain, reflexion coefficients S 11 , S 22 < -30 dB over the 2.4 GHz ISM band, a peak noise figure of 1.8 dB, and an IIP 3 of 1 dBm, while drawing less than 4.5 mA dc biasing current from the 1.2 V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to plusmn2.0 kV, by means of the additional custom protection circuitry.Comisión Interministerial de Ciencia y Tecnología TIC2003-02355Ministerio de Educación y Ciencia TEC2006-0302

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

page number: 12International audienceWith the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins

Investigations on electromagnetic noises and interactions in electronic architectures : a tutorial case on a mobile system

Electromagnetic interactions become critic in embedded and smart electronic structures. The increase of electronic performances confined in a finite volume or support for mobile applications defines new electromagnetic environment and compatibility configurations (EMC). With canonical demonstrators developed for tutorials and EMC experiences, this paper present basic principles and experimental techniques to investigate and control these severe interferences. Some issues are reviewed to present actual and future scientific challenges for EMC at electronic circuit level

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

Understanding, modeling, and mitigating system-level ESD in integrated circuits

This dissertation describes several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important tool for achieving quality designs quickly. However, modeling methodologies for system-level ESD are not yet mature. This dissertation aims to improve (i) simulation models of ESD protection elements, (ii) simulation models of ESD guns, and (iii) analytic models of rail-clamp circuits used for power-on ESD protection. Simulation models for two common ESD protection elements, diodes and silicon controlled rectifiers (SCR) are presented and evaluated, specifically with regard to the origins of poor voltage clamping. These models can be used for ESD network design and simulation; their applicability is not limited only to system-level ESD. Next, a circuit simulation model for an ESD gun (used to produce system-level ESD stresses) is presented. This model can be used for trouble-shooting and design. Lastly, an analytic model of rail-clamp circuits during system-level ESD is presented. These circuits can produce unstable oscillations or ringing on the supply; such problems must be eliminated during design. Analytic models help the designer understand how circuit parameters will impact the circuit’s performance. System-level ESD is a relatively new requirement being imposed on IC manufacturers; as such, current understanding of how system-level ESD affects ICs is not yet mature. This dissertation includes two studies that expand upon this knowledge. The first demonstrates that ground bounce due system-level ESD stress can lead to severe problems, including latch-up and power integrity problems. The second reports observations regarding input noise signals at an IC pin during system-level ESD stress. Lastly, this dissertation discusses experimental design of a test chip that will be manufactured shortly after this dissertation is completed. These experiments focus on observing and suppressing various errors that can occur during system-level ESD, arising from both noise at the inputs and power fluctuations. Additionally, this test chip includes standalone test structures that are used to reproduce power supply problems predicted in other sections of this dissertation

ESD related soft error detection and root cause analysis

In this article, several methods are outlined for detecting functional changes in an IC due to external interference such as ESD or EMI. The goal is to provide diagnostic tools for detection of potential soft failure susceptibilities of complex systems during the hardware design stage without the aid of any complex software. After the soft errors are found, circuit modeling techniques are used to characterize the DUT. By running the circuit model, the soft error threshold can be predicted and the circuit model can be used to evaluate the performance of other ESD protection methods. In the end several methods are used to separate local soft-failures from distant errors related to noise on the power distribution network (PDN) is demonstrated. Two approaches are used, one passive and one active, which duplicate the noise on a system PDN caused by some intentional injection onto a second system where the intentional injection is not present --Abstract, page iii

CMOS RF low noise amplifier with high ESD immunity.

Tang Siu Kei.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 107-111).Abstracts in English and Chinese.Acknowledgements --- p.iiAbstract --- p.iiiList of Figures --- p.xiList of Tables --- p.xviChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4Chapter 1.3 --- Research Goal and Contribution --- p.6Chapter 1.4 --- Thesis Outline --- p.6Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8Chapter 2.1 --- Amplifier Gain --- p.8Chapter 2.2 --- Noise Factor --- p.9Chapter 2.3 --- Linearity --- p.11Chapter 2.3.1 --- 1-dB Compression Point --- p.13Chapter 2.3.2 --- Third-Order Intercept Point --- p.14Chapter 2.4 --- Return Loss --- p.16Chapter 2.5 --- Power Consumption --- p.18Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21Chapter 3.1 --- Dual-Diode Circuitry --- p.22Chapter 3.1.1 --- Working Principle --- p.22Chapter 3.1.2 --- Drawbacks --- p.24Chapter 3.2 --- Shunt-Inductor Method --- p.25Chapter 3.2.1 --- Working Principle --- p.25Chapter 3.2.2 --- Drawbacks --- p.27Chapter 3.3 --- Common-Gate Input Stage Method --- p.28Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29Chapter 3.3.2 --- Competitiveness --- p.31Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32Chapter 4.1 --- Small-Signal Modeling --- p.33Chapter 4.2 --- Method of Input Termination --- p.33Chapter 4.2.1 --- Resistive Termination --- p.34Chapter 4.2.2 --- Shunt-Series Feedback --- p.34Chapter 4.2.3 --- l/gm Termination --- p.35Chapter 4.2.4 --- Inductive Source Degeneration --- p.36Chapter 4.3 --- Method of Gain Enhancement --- p.38Chapter 4.3.1 --- Tuned Amplifier --- p.38Chapter 4.3.2 --- Multistage Amplifier --- p.40Chapter 4.4 --- Improvement of Reverse Isolation --- p.41Chapter 4.4.1 --- Common-Gate Amplifier --- p.41Chapter 4.4.2 --- Cascoded Amplifier --- p.42Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55Chapter 6.2 --- Design of Two-Stage Architecture --- p.57Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59Chapter 6.3 --- Stability Consideration --- p.61Chapter 6.4 --- Design of Matching Networks --- p.62Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67Chapter Chapter 7 --- Layout Considerations --- p.70Chapter 7.1 --- MOS Transistor --- p.70Chapter 7.2 --- Capacitor --- p.72Chapter 7.3 --- Spiral Inductor --- p.74Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81Chapter Chapter 8 --- Measurement Results --- p.82Chapter 8.1 --- Experimental Setup --- p.82Chapter 8.1.1 --- Testing Circuit Board --- p.83Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89Chapter 8.2.1 --- S-parameter Measurement --- p.90Chapter 8.2.2 --- Noise Figure Measurement --- p.91Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93Chapter 8.2.5 --- HBM ESD Test --- p.94Chapter 8.2.6 --- Summary of Measurement Results --- p.95Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96Chapter 8.3.1 --- s-parameter Measurement --- p.97Chapter 8.3.2 --- Noise Figure Measurement --- p.98Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100Chapter 8.3.5 --- HBM ESD Test --- p.101Chapter 8.3.6 --- Summary of Measurement Results --- p.102Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103Chapter Chapter 9 --- Conclusion and Future Work --- p.105Chapter 9.1 --- Conclusion --- p.105Chapter 9.2 --- Future Work --- p.106References --- p.107Author's Publications --- p.11

Characterisation of on-chip electrostatic discharge waveforms with sub-nanosecond resolution: design of a differential high voltage probe with high bandwidth

Bliksem werd tot aan de ontdekking van de bliksemafleider (18e eeuw) gezien als een van de gevaarlijkste bedreigingen voor het stadsleven. Door het gebruik van micro-elektronica werden ingenieurs gewaar dat ditzelfde fysische verschijnsel, elektrostatische ontlading of ESD genoemd, zich ook op microscopische schaal voordoet. In de jaren zeventig was meer dan 30% van al het chipfalen te wijten aan ESD. Om dit tegen te gaan werd met het onderzoek naar ESD-protecties en -meetsystemen aangevangen. Om meer informatie over het gedrag van een ESD-protectie te verkrijgen wordt een ESD-puls op dit systeem losgelaten. Het antwoord van de protectie op deze puls wordt dan bepaald m.b.v. spannings- en stroomgolfvormmetingen. In dit werk wordt een nieuwe nauwkeurige ESD-golfvormmeettechniek voorgesteld die directe metingen op protecties kan uitvoeren. De karakterisering van ESD-golfvormen op chip wordt enorm bemoeilijkt door de grote hoeveelheid elektromagnetische interferentie die de ESD-puls veroorzaakt. Dit wordt omzeild door het gewenste signaal naar een veilige omgeving te transporteren, waar een standaard meettoestel de meting kan uitvoeren. Dit transport wordt gerealiseerd m.b.v. optische communicatie, wat immuun is voor elektromagnetische interferentie. Zo kan nauwkeurige in-situ-informatie worden verkregen waarmee de ESD-protecties in de toekomst verbeterd kunnen worden.Up to the 18th century, lightning was considered one of nature’s most dangerous threats in city life. This all ended with the lightning rod, protecting thousands of homes during lightning storms. The large-scale use of microelectronics has made engineers aware of the same physical phenomenon occuring on a microscopic scale. This phenomenon is called electrostatic discharge or ESD. In the seventies, more than 30% of all chip failure was attributed to static electricity. To counter this effect, the research for on-chip ESD protections was born. Today ESD is a buzzing line of research, as with new and faster chip technologies comes a higher ESD vulnerability. This makes ESD protection and measurement increasingly important. Although ESD is now a major subject in chip design, it copes with a lack of accurate device models. To gain more information on the exact operation of an ESD protection, an ESD pulse is unleashed upon this device. The response of the protection on this pulse is then assessed by performing voltage or current waveform measurements. This work presents a waveform measurement technique able to accurately perform direct measurements on the ESD protection. Due to the high amount of electromagnetic interference caused by the ESD pulse, direct waveform characterisation near the protection is hard. This is solved by transporting the target signal into a clean area, where the measurement is performed by standard lab equipment. The key is that this transportation is realized by means of optical communication, which is immune to electromagnetic interference. This way, accurate in situ information can be used to protect tomorrow’s chips

Design for Electromagnetic Compatibility--In a Nutshell

This open access book provides practicing electrical engineers and students a practical – and mathematically sound – introduction to the topic of electromagnetic compatibility (EMC). The author enables readers to understand better how to overcome commonly failed EMC tests for radiated emission, radiated immunity, and electrostatic discharge (ESD), while providing concrete EMC design guidelines. The book also presents an overview of EMC standards and regulations and how to test for a global market access