Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

IC design for reliability

textAs the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.Electrical and Computer Engineerin

Collective dynamics of belief evolution under cognitive coherence and social conformity

Human history has been marked by social instability and conflict, often driven by the irreconcilability of opposing sets of beliefs, ideologies, and religious dogmas. The dynamics of belief systems has been studied mainly from two distinct perspectives, namely how cognitive biases lead to individual belief rigidity and how social influence leads to social conformity. Here we propose a unifying framework that connects cognitive and social forces together in order to study the dynamics of societal belief evolution. Each individual is endowed with a network of interacting beliefs that evolves through interaction with other individuals in a social network. The adoption of beliefs is affected by both internal coherence and social conformity. Our framework explains how social instabilities can arise in otherwise homogeneous populations, how small numbers of zealots with highly coherent beliefs can overturn societal consensus, and how belief rigidity protects fringe groups and cults against invasion from mainstream beliefs, allowing them to persist and even thrive in larger societies. Our results suggest that strong consensus may be insufficient to guarantee social stability, that the cognitive coherence of belief-systems is vital in determining their ability to spread, and that coherent belief-systems may pose a serious problem for resolving social polarization, due to their ability to prevent consensus even under high levels of social exposure. We therefore argue that the inclusion of cognitive factors into a social model is crucial in providing a more complete picture of collective human dynamics

Offset balancing in pseudo-correlation radiometers for CMB measurements

Radiometeric CMB measurements need to be highly stable and this stability is best obtained with differential receivers. The residual 1/f noise in the differential output is strongly dependent on the radiometer input offset which can be cancelled using various balancing strategies. In this paper we discuss a software method implemented in the Planck-LFI pseudo-correlation receivers which uses a tunable "gain modulation factor, r, in the sky-load difference. Numerical simulations and experimental data show how proper tuning of the parameter r ensures a very stable differential output with knee frequencies of the order of few mHz. Various approaches to calculate r using the radiometer total power data are discussed with some examples relevant to Planck-LFI. Although the paper focuses on pseudo-correlation receivers and the examples are relative to Planck-LFI, the proposed method and its analysis is general and can be applied to a large class of differential radiometric receivers.Comment: 12 pages, 8 figures, accepted for publication in A&A (updated version with few editorial changes

Fermi-surface topological phase transition and horizontal order-parameter nodes in CaFe2_2As2_2 under pressure

Iron-based compounds (IBS) display a surprising variety of superconducting properties that seems to arise from the strong sensitivity of these systems to tiny details of the lattice structure. In this respect, systems that become superconducting under pressure, like CaFe$_2$As$_2$, are of particular interest. Here we report on the first directional point-contact Andreev-reflection spectroscopy (PCARS) measurements on CaFe$_2$As$_2$ crystals under quasi-hydrostatic pressure, and on the interpretation of the results using a 3D model for Andreev reflection combined with ab-initio calculations of the Fermi surface (within the density functional theory) and of the order parameter symmetry (within a random-phase-approximation approach in a ten-orbital model). The almost perfect agreement between PCARS results at different pressures and theoretical predictions highlights the intimate connection between the changes in the lattice structure, a topological transition in the hole-like Fermi surface sheet, and the emergence on the same sheet of an order parameter with a horizontal node line.Comment: 13 pages, 8 color figures. This is an author-created, un-copyedited version of an article published in Scientific Reports. The published version is available online, together with Supplementary Information, at http://www.nature.com/articles/srep2639

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling(DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI)in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead

The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology

On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are

inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices

Transistor technology scaling has been the driving force in improving the size, speed, and power consumption of digital systems. As devices approach atomic size, however, their reliability and performance are increasingly compromised due to reduced noise margins, difficulties in fabrication, and emergent nano-scale phenomena. Scaled CMOS devices, in particular, suffer from process variations such as random dopant fluctuation (RDF) and line edge roughness (LER), transistor degradation mechanisms such as negative-bias temperature instability (NBTI) and hot-carrier injection (HCI), and increased sensitivity to single event upsets (SEUs). Consequently, future devices may exhibit reduced performance, diminished lifetimes, and poor reliability. This research proposes a variation and fault tolerant architecture, the inSense architecture, as a circuit-level solution to the problems induced by the aforementioned phenomena. The inSense architecture entails augmenting circuits with introspective and sensory capabilities which are able to dynamically detect and compensate for process variations, transistor degradation, and soft errors. This approach creates ``smart\u27\u27 circuits able to function despite the use of unreliable devices and is applicable to current CMOS technology as well as next-generation devices using new materials and structures. Furthermore, this work presents an automated prototype implementation of the inSense architecture targeted to CMOS devices and is evaluated via implementation in ISCAS \u2785 benchmark circuits. The automated prototype implementation is functionally verified and characterized: it is found that error detection capability (with error windows from $\approx$30-400ps) can be added for less than 2\% area overhead for circuits of non-trivial complexity. Single event transient (SET) detection capability (configurable with target set-points) is found to be functional, although it generally tracks the standard DMR implementation with respect to overheads

Techniques for Aging, Soft Errors and Temperature to Increase the Reliability of Embedded On-Chip Systems

This thesis investigates the challenge of providing an abstracted, yet sufficiently accurate reliability estimation for embedded on-chip systems. In addition, it also proposes new techniques to increase the reliability of register files within processors against aging effects and soft errors. It also introduces a novel thermal measurement setup that perspicuously captures the infrared images of modern multi-core processors

Impact of aging on the soft error rate of 6T SRAM for planar and bulk technologies

This paper evaluates the impact of aging on the radiation sensitivity of 6T SRAMfor two planar bulk technologies. This study ismotivated by the growing impact of aging and radiation effects on the reliability of CMOS technology. Amodelling methodology dedicated to this newphenomenon is proposed. Thismodelling uses the radiation modelling device MUSCA SEP3 and an electrical aging modelling. First, the impact of aging on SEE sensitivity is studied through a parametric modeling of the threshold voltages of the transistors composing the 6T SRAM. Then, an operative avionics environment is modelled in order to evaluate the consequences on reliability