13,708 research outputs found

    Techniques for Aging, Soft Errors and Temperature to Increase the Reliability of Embedded On-Chip Systems

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    This thesis investigates the challenge of providing an abstracted, yet sufficiently accurate reliability estimation for embedded on-chip systems. In addition, it also proposes new techniques to increase the reliability of register files within processors against aging effects and soft errors. It also introduces a novel thermal measurement setup that perspicuously captures the infrared images of modern multi-core processors

    Low-temperature anomalies of a vapor deposited glass

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    We investigate the low temperature properties of two-dimensional Lennard-Jones glass films, prepared in silico both by liquid cooling and by physical vapor deposition. We identify deep in the solid phase a crossover temperature T∗T^*, at which slow dynamics and enhanced heterogeneity emerge. Around T∗T^*, localized defects become visible, leading to vibrational anomalies as compared to standard solids. We find that on average, T∗T^* decreases in samples with lower inherent structure energy, suggesting that such anomalies will be suppressed in ultra-stable glass films, prepared both by very slow liquid cooling and vapor deposition.Comment: 10 pages including appendices, 8 figures. Version accepted for Physical Review Material

    Impact of Bias Temperature Instability on Soft Error Susceptibility

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    In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

    Glassy dynamics and dynamical heterogeneity in colloids

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    Concentrated colloidal suspensions are a well-tested model system which has a glass transition. Colloids are suspensions of small solid particles in a liquid, and exhibit glassy behavior when the particle concentration is high; the particles are roughly analogous to individual molecules in a traditional glass. Because the particle size can be large (100 nm - 1000 nm), these samples can be studied with a variety of optical techniques including microscopy and dynamic light scattering. Here we review the phenomena associated with the colloidal glass transition, and in particular discuss observations of spatial and temporally heterogeneous dynamics within colloidal samples near the glass transition. Although this Chapter focuses primarily on results from hard-sphere-like colloidal particles, we also discuss other colloidal systems with attractive or soft repulsive interactions.Comment: Chapter of "Dynamical heterogeneities in glasses, colloids, and granular media", Eds.: L. Berthier, G. Biroli, J-P Bouchaud, L. Cipelletti and W. van Saarloos (Oxford University Press, to appear), more info at http://w3.lcvn.univ-montp2.fr/~lucacip/DH_book.ht

    Numerical detection of the Gardner transition in a mean-field glass former

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    Recent theoretical advances predict the existence, deep into the glass phase, of a novel phase transition, the so-called Gardner transition. This transition is associated with the emergence of a complex free energy landscape composed of many marginally stable sub-basins within a glass metabasin. In this study, we explore several methods to detect numerically the Gardner transition in a simple structural glass former, the infinite-range Mari-Kurchan model. The transition point is robustly located from three independent approaches: (i) the divergence of the characteristic relaxation time, (ii) the divergence of the caging susceptibility, and (iii) the abnormal tail in the probability distribution function of cage order parameters. We show that the numerical results are fully consistent with the theoretical expectation. The methods we propose may also be generalized to more realistic numerical models as well as to experimental systems.Comment: 17 pages, 16 figure

    Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

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    In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling(DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI)in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead

    The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology

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    On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are

    Impact of aging on the soft error rate of 6T SRAM for planar and bulk technologies

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    This paper evaluates the impact of aging on the radiation sensitivity of 6T SRAMfor two planar bulk technologies. This study ismotivated by the growing impact of aging and radiation effects on the reliability of CMOS technology. Amodelling methodology dedicated to this newphenomenon is proposed. Thismodelling uses the radiation modelling device MUSCA SEP3 and an electrical aging modelling. First, the impact of aging on SEE sensitivity is studied through a parametric modeling of the threshold voltages of the transistors composing the 6T SRAM. Then, an operative avionics environment is modelled in order to evaluate the consequences on reliability

    Aging Benefits in Nanometer CMOS Designs

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    This document is the Accepted Manuscript version of the following article: Daniele Rossi, Vasileios Tenentes, Sheng Yang, Saqib Khursheed, and Bashir M. Al-Hashimi, ‘Aging Benefits in Nanometer CMOS Designs’, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64 (3), May 2016. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.n this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.Peer reviewedFinal Accepted Versio
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