A Survey of Positioning Systems Using Visible LED Lights

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.As Global Positioning System (GPS) cannot provide satisfying performance in indoor environments, indoor positioning technology, which utilizes indoor wireless signals instead of GPS signals, has grown rapidly in recent years. Meanwhile, visible light communication (VLC) using light devices such as light emitting diodes (LEDs) has been deemed to be a promising candidate in the heterogeneous wireless networks that may collaborate with radio frequencies (RF) wireless networks. In particular, light-fidelity has a great potential for deployment in future indoor environments because of its high throughput and security advantages. This paper provides a comprehensive study of a novel positioning technology based on visible white LED lights, which has attracted much attention from both academia and industry. The essential characteristics and principles of this system are deeply discussed, and relevant positioning algorithms and designs are classified and elaborated. This paper undertakes a thorough investigation into current LED-based indoor positioning systems and compares their performance through many aspects, such as test environment, accuracy, and cost. It presents indoor hybrid positioning systems among VLC and other systems (e.g., inertial sensors and RF systems). We also review and classify outdoor VLC positioning applications for the first time. Finally, this paper surveys major advances as well as open issues, challenges, and future research directions in VLC positioning systems.Peer reviewe

The Utilization of Artificial Neural Network Equalizer in Optical Camera Communications

In this paper, we propose and validate an artificial neural network-based equalizer for the constant power 4-level pulse amplitude modulation in an optical camera communications system. We introduce new terminology to measure the quality of the communications link in terms of the number of row pixels per symbol , which allows a fair comparison considering the progress made in the development of the current image sensors in terms of the frame rates and the resolutions of each frame. Using the proposed equalizer, we experimentally demonstrate a non-flickering system using a single light-emitting diode (LED) with of 20 and 30 pixels/symbol for the unequalized and equalized systems, respectively. Potential transmission rates of up to 18.6 and 24.4 kbps are achieved with and without the equalization, respectively. The quality of the received signal is assessed using the eye-diagram opening and its linearity and the bit error rate performance. An acceptable bit error rate (below the forward error correction limit) and an improvement of ~66 in the eye linearity are achieved using a single LED and a typical commercial camera with equalization

VISUAL LIGHT COMMUNICATION USING IMAGE PROCESSING IN OPENCL

This project explored the use of cameras and image-processing programs to establish a visible light communications link. The system, which consisted of a Raspberry Pi that drove a red-light emitting diode and camera, was connected via transmission control protocol to a graphics-processing unit with an OpenCL image-processing program used to decode the transmission. The system achieved a maximum data transfer rate of 10.0 bits per second with 0.005 bit error ratio with one LED. It achieved a maximum data rate of 20.0 bps with 0.143 bit error ratio with two LEDs. The system performance is limited by the low frame rate of the Raspberry Pi camera. Further improvements could include replacing the camera with a high-speed device to increase the data rate and improving the system’s resilience to interference.Ensign, United States NavyApproved for public release; distribution is unlimited

High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics

This dissertation describes the schematic design, physical layout implementation, system-level hardware with FPGA firmware design, and testing of a camera-on-a-chip with a novel high-speed CMOS image sensor (CIS) architecture developed for a mega-pixel array. The novel features of the design include an innovative quadruple column-parallel readout (QCPRO) scheme with rolling shutter that increases pixel rate, its ability to program the frame rate and to tolerate Total Ionizing Dose effects (TID). Two versions of the architecture, a small (128 x 1,024 pixels) and large (768 x 1,024 pixels) version were designed and fabricated with a custom layout that does not include library parts. The designs achieve a performance of 20 to 4,000 frames per second (fps) and they tolerate up to 125 krads of radiation exposure. The high-speed CIS architecture proposes and implements a creative quadruple column-parallel readout (QCPRO) scheme to achieve a maximum pixel rate, 10.485 gigapixels/s. The QCPRO scheme consists of four readout blocks per column and to complete four rows of pixels readout process at one line time. Each column-level readout block includes an analog time-interleaving (ATI) sampling circuit, a switched-capacitor programmable gain amplifier (SC-PGA), a 10-bit successive-approximation register (SAR) ADC, two 10-bit memory banks. The column-parallel SAR ADC is area-efficient to be laid out in half of one pixel pitch, 10 um. The analog ATI sampling circuit has two sample-and-hold circuits. Each sampling circuit can independently complete correlated double sampling (CDS) operation. Furthermore, to deliver over 10^10 pixel data in one second, a high-speed differential Scalable Low-Voltage Signaling (SLVS) transmitter for every 16 columns is designed to have 1 Gbps/ch at 0.4 V. Two memory banks provide a ping-pong operation: one connecting to the ADC for storing digital data and the other to the SLVS for delivering data to the off-chip FPGA. Therefore, the proposed CIS architecture can achieve 10,000 frames per second for a 1,024 x 1,024 pixel array. The floor plan of the proposed CIS architecture is symmetrical having one-half of pixel rows to read out on top, and the other half read out on the bottom of the pixel array. The rolling shutter feature with multi-lines readout in parallel and oversampling technique relaxes the image artifacts for capturing fast-moving objects. The CIS camera can provide complete digital input control and digital pixel data output. Many other components are designed and integrated into the proposed CMOS imager, including the Serial Peripheral Interface (SPI), bandgap reference, serializers, phase-locked loops (PLLs), and sequencers with configuration registers. Also, the proposed CIS can program the frame rate for wider applications by modifying three parameters: input clock frequency, the region of interest, and the counter size in the sequencer. The radiation hardening feature is achieved by using the combination of enclosed geometry technique and P-type guard-rings in the 0.18 um CMOS technology. The peripheral circuits use P-type guard-rings to cut the TID-induced leakage path between device to device. Each pixel cell is radiation tolerant by using enclosed layout transistors. The pinned photodiode is also used to get low dark current, and correlated double sampling to suppress pixel-level fixed-pattern noise and reset noise. The final pixel cell is laid out in 20 x 20 um^2. The total area of the pixel array is 2.56 x 20.28 mm^2 for low-resolution imager prototype and 15.36 x 20.28 mm^2 for high-resolution imager prototype. The entire CIS camera system is developed by the implementation of the hardware and FPGA firmware of the small-format prototype with 128 x 1,024 pixels and 754 pads in a 4.24 x 25.125 mm^2 die area. Different testing methods are also briefly described for different test purposes. Measurement results validate the functionalities of the readout path, sequencer, on-chip PLLs, and the SLVS transmitters. The programmable frame rate feature is also demonstrated by checking the digital control outputs from the sequencer at different frame rates. Furthermore, TID radiation tests proved the pixels can work under 125 krads radiation exposure

Visible Light Optical Camera Communication for Electroencephalography Applications

Due to the cable-free deployment and flexibility of wireless communications, the data transmission in the applications of home and healthcare has shown a trend of moving wired communications to wireless communications. One typical example is electroencephalography (EEG). Evolution in the radio frequency (RF) technology has made it is possible to transmit the EEG data without data cable bundles. However, presently, the RF-based wireless technology used in EEG suffers from electromagnetic interference and might also have adverse effects on the health of patient and other medical equipment used in hospitals or homes. This puts some limits in RF-based EEG solutions, which is particularly true in RF restricted zones like Intensive Care Units (ICUs). As a recently developed optical wireless communication (OWC) technology, visible light communication (VLC) using light-emitting diodes (LEDs) for both simultaneous illumination and data communication has shown its advantages of free from electromagnetic interference, potential huge unlicensed bandwidth and enhanced data privacy due to the line transmission of light. The most recent development of VLC is the optical camera communication (OCC), which is an extension of VLC IEEE standard 802.15.7, also referred to as visible light optical camera communication (VL-OCC). Different from the conventional VLC where traditional photodiodes are used to detect and receive the data, VL-OCC uses the imaging camera as the photodetector to receive the data in the form of visible light signals. The data rate requirement of EEG is dependent on the application; hence this thesis investigates a low cost, organic LED (OLED)-driven VL-OCC wireless data transmission system for EEG applications