A Wafer Bin Map "Relaxed" Clustering Algorithm for Improving Semiconductor Production Yield

AbstractThe semiconductor manufacturing process involves long and complex activities, with intensive use of resources. Producers compete through the introduction of new technologies for increasing yield and reducing costs. So, yield improvement is becoming increasingly important since advanced production technologies are complex and interrelated. In particular, Wafer Bin Maps (WBMs) presenting specific fault models provide crucial information to keep track of process problems in semiconductor manufacturing. Production control is often based on the "judgement" of expert engineers who, however, carry out the analysis of map templates through simple visual exploration. In this way, existing studies are subjective, time consuming, and are also limited by the capacity of human recognition. This study proposes a network-based data mining approach, which integrates correlation graphs with clustering analysis to quickly extract patterns from WBMs and then bind them to manufacturing defects. An empirical study has been conducted on real production data for validating the proposed clustering algorithm, which showed a perfect correspondence between the malfunction patterns found by the algorithm and those discovered by human experts, so confirming the validity of our approach in its ability of correctly identifying actual defective patterns to help improving production yield

A review of data mining applications in semiconductor manufacturing

The authors acknowledge Fundacao para a Ciencia e a Tecnologia (FCT-MCTES) for its financial support via the project UIDB/00667/2020 (UNIDEMI).For decades, industrial companies have been collecting and storing high amounts of data with the aim of better controlling and managing their processes. However, this vast amount of information and hidden knowledge implicit in all of this data could be utilized more efficiently. With the help of data mining techniques unknown relationships can be systematically discovered. The production of semiconductors is a highly complex process, which entails several subprocesses that employ a diverse array of equipment. The size of the semiconductors signifies a high number of units can be produced, which require huge amounts of data in order to be able to control and improve the semiconductor manufacturing process. Therefore, in this paper a structured review is made through a sample of 137 papers of the published articles in the scientific community regarding data mining applications in semiconductor manufacturing. A detailed bibliometric analysis is also made. All data mining applications are classified in function of the application area. The results are then analyzed and conclusions are drawn.publishersversionpublishe

Defect cluster recognition system for fabricated semiconductor wafers

The International Technology Roadmap for Semiconductors (ITRS) identifies production test data as an essential element in improving design and technology in the manufacturing process feedback loop. One of the observations made from the high-volume production test data is that dies that fail due to a systematic failure have a tendency to form certain unique patterns that manifest as defect clusters at the wafer level. Identifying and categorising such clusters is a crucial step towards manufacturing yield improvement and implementation of real-time statistical process control. Addressing the semiconductor industry's needs, this research proposes an automatic defect cluster recognition system for semiconductor wafers that achieves up to 95% accuracy (depending on the product type)

The Dark Energy Survey

We describe the Dark Energy Survey (DES), a proposed optical-near infrared survey of 5000 sq. deg of the South Galactic Cap to ~24th magnitude in SDSS griz, that would use a new 3 sq. deg CCD camera to be mounted on the Blanco 4-m telescope at Cerro Telolo Inter-American Observatory (CTIO). The survey data will allow us to measure the dark energy and dark matter densities and the dark energy equation of state through four independent methods: galaxy clusters, weak gravitational lensing tomography, galaxy angular clustering, and supernova distances. These methods are doubly complementary: they constrain different combinations of cosmological model parameters and are subject to different systematic errors. By deriving the four sets of measurements from the same data set with a common analysis framework, we will obtain important cross checks of the systematic errors and thereby make a substantial and robust advance in the precision of dark energy measurements.Comment: White Paper submitted to the Dark Energy Task Force, 42 page

Advanced Process Monitoring for Industry 4.0

This book reports recent advances on Process Monitoring (PM) to cope with the many challenges raised by the new production systems, sensors and “extreme data” conditions that emerged with Industry 4.0. Concepts such as digital-twins and deep learning are brought to the PM arena, pushing forward the capabilities of existing methodologies to handle more complex scenarios. The evolution of classical paradigms such as Latent Variable modeling, Six Sigma and FMEA are also covered. Applications span a wide range of domains such as microelectronics, semiconductors, chemicals, materials, agriculture, as well as the monitoring of rotating equipment, combustion systems and membrane separation processes

A deep learning-based approach for defect classification with context information in semiconductor manufacturing

This thesis presents some methodological and experimental contributions to a deep learning-based approach for the automatic classifi cation of microscopic defects in silicon wafers with context information. Canonical image classifi cation approaches have the limitation of utilizing only the information contained in the images. This work overcomes this limitation by using some context information about the defects to improve the current automatic classifi cation system

On the design and implementation of a wafer yield editor

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and is able to predict wafer yields via simple simulation tools. An analysis approach based on site yields makes the system independent of the product and of the technology. The analysis technique makes it possible to investigate the effects of both correlated and uncorrelated sources of yield loss. The statistical information obtained can be used to study changes in the technological process. Graphical displays in the form of wafer maps are used to represent the spatial distribution of dice in the wafer. Capabilities for such as radial and angular distribution analyses, among others, are provided to examine data, and hypothetical wafer maps are created to visualize and predict simulated wafer yield

Course development in IC manufacturing

A traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management and the study of random process variations impacting circuit behaviour are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University, USA, to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufacturability. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semeste

Integrated circuit outlier identification by multiple parameter correlation

Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed