A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Phase Dependency of the Human Primary Motor Cortex and Cholinergic Inhibition Cancelation during Beta tACS

The human motor cortex has a tendency to resonant activity at about 20 Hz so stimulation should more readily entrain neuronal populations at this frequency. We investigated whether and how different interneuronal circuits contribute to such resonance by using transcranial magnetic stimulation (TMS) during transcranial alternating current stimulation (tACS) at motor (20 Hz) and a nonmotor resonance frequency (7 Hz). We tested different TMS interneuronal protocols and triggered TMS pulses at different tACS phases. The effect of cholinergic short-latency afferent inhibition (SAI) was abolished by 20 Hz tACS, linking cortical beta activity to sensorimotor integration. However, this effect occurred regardless of the tACS phase. In contrast, 20 Hz tACS selectively modulated MEP size according to the phase of tACS during single pulse, GABAAergic short-interval intracortical inhibition (SICI) and glutamatergic intracortical facilitation (ICF). For SICI this phase effect was more marked during 20 Hz stimulation. Phase modulation of SICI also depended on whether or not spontaneous beta activity occurred at ~20 Hz, supporting an interaction effect between tACS and underlying circuit resonances. The present study provides in vivo evidence linking cortical beta activity to sensorimotor integration, and for beta oscillations in motor cortex being promoted by resonance in GABAAergic interneuronal circuits

Time representation in reinforcement learning models of the basal ganglia

Reinforcement learning (RL) models have been influential in understanding many aspects of basal ganglia function, from reward prediction to action selection. Time plays an important role in these models, but there is still no theoretical consensus about what kind of time representation is used by the basal ganglia. We review several theoretical accounts and their supporting evidence. We then discuss the relationship between RL models and the timing mechanisms that have been attributed to the basal ganglia. We hypothesize that a single computational system may underlie both RL and interval timing—the perception of duration in the range of seconds to hours. This hypothesis, which extends earlier models by incorporating a time-sensitive action selection mechanism, may have important implications for understanding disorders like Parkinson's disease in which both decision making and timing are impaired

WIMAX 802.16 PHYSICAL LAYER IMPLEMENTATION AND WIMAX COVERAGE AND PLANNING.

Over the last decade, the impact of wireless communication on the way we live and carry out business has been surpassed only by impact of the internet. But wireless communications is still in its infancy and the next stage of its development will be supplementing or replacing network infrastructure that was traditionally wired. The advent and adoption of the computer and the myriad software packages available for it offered the ability to generate a new wave of communication combining art, pictures, music and words into a targeted multimedia presentation. These presentations are large so that is requires higher bandwidth transmission facilities. Coupling this with the need for mobility, the solution would be wireless data delivery putting in consideration the bandwidth request. WiMAX technology is based on the IEEE 802.16 standard, it was only recently when the first IEEE 802.16 based equipment broadband began to enter the market. The additional spectrum, bandwidth and throughout capabilities of 802.16 will remarkably improve wireless data delivery and should allows even more wireless data service areas to be deployed economically. In this Final Year Project, a study about the IEEE 802.16 standard and mainly concentrate on the 802.16 PHY Layer behaviors was performed. A Simulink based model for the 802.16 PHY Layer was built for simulation and performance evaluation of WiMAX. MATLA

Analysis Of Time Synchronization Errors In High Data Rate Ultrawideban

Emerging Ultra Wideband (UWB) Orthogonal Frequency Division Multiplexing (OFDM) systems hold the promise of delivering wireless data at high speeds, exceeding hundreds of megabits per second over typical distances of 10 meters or less. The purpose of this Thesis is to estimate the timing accuracies required with such systems in order to achieve Bit Error Rates (BER) of the order of magnitude of 10-12 and thereby avoid overloading the correction of irreducible errors due to misaligned timing errors to a small absolute number of bits in error in real-time relative to a data rate of hundreds of megabits per second. Our research approach involves managing bit error rates through identifying maximum timing synchronization errors. Thus, it became our research goal to determine the timing accuracies required to avoid operation of communication systems within the asymptotic region of BER flaring at low BERs in the resultant BER curves. We propose pushing physical layer bit error rates to below 10-12 before using forward error correction (FEC) codes. This way, the maximum reserve is maintained for the FEC hardware to correct for burst as well as recurring bit errors due to corrupt bits caused by other than timing synchronization errors