A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

International audienceWith the explosion of advanced power control knobs such as dynamic voltage frequency scaling, mastering energy constraints in embedded systems is becoming challenging for software developers. Several power estimation techniques have been proposed over the past years, from electrical level to more abstract models such as SystemC/TLM. They offer various trade-offs between performance and accuracy, but suffer from a number of shortcomings. They are expensive and time-consuming, requiring intricate models of the architecture and finally, fail to be applied from the software developer perspective. In this paper, we propose a lightweight and cost-effective approach suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without loosing accuracy. This approach is fully supported by a tool and is validated using a simple thermal mitigation case study and checked against physical measurements. We show that, for our case study, the relative error between our tool and real values is 8% in average

IP-XACT for Smart Systems Design: Extensions for the Integration of Functional and Extra-Functional Models

Smart systems are miniaturized devices integrating computation, communication, sensing and actuation. As such, their design can not focus solely on functional behavior, but it must rather take into account different extra-functional concerns, such as power consumption or reliability. Any smart system can thus be modeled through a number of views, each focusing on a specific concern. Such views may exchange information, and they must thus be simulated simultaneously to reproduce mutual influence of the corresponding concerns. This paper shows how the IP-XACT standard, with some necessary extensions, can effectively support this simultaneous simulation. The extended IP-XACT descriptions allow to model extra-functional properties with a homogeneous format, defined by analysing requirements and characteristic of three main concerns, i.e., power, temperature and reliability. The IP-XACT descriptions are then used to automatically generate a skeleton of the simulation infrastructure in SystemC. The skeleton can be easily populated with models available in the literature, thus reaching simultaneous simulation of multiple concerns

A generic debug interface for IP-integrated assertions

Der Entwurf von Hardware/Software Systemen ist auf eine solide Verifikationsmethodik angewiesen, die den ganzen Design Flow durchzieht. Viele Konzepte haben eine Erhöhung des Abstraktionsniveaus bei der Entwurfseingabe gemeinsam, wobei der modell-basierte Hardware-Entwurf einen vielversprechenden und sich verbreitenenden Ansatz darstellt. Assertion basierte Verifikation ermöglicht dem Entwickler die Spezifikation von Eigenschaften des Entwurfes und die Aufdeckung von Fällen, in denen diese verletzt werden. Während Assertions in Entwurfs- und Simulationsstadien weit verbreitet sind, ist der Ansatz, diese mit auf dem integrierten Schaltkreis (IC) zu fertigen, neuartig. In dieser Diplomarbeit soll ein von Infineon Technologies entwickeltes, auf UML basierendes Datenmodell, welches zur Erfassung von Entwurfsspezifikation und zur automatischen Code-Generierung genutzt wird dahingehend erweitert werden, die Beschreibung für im IC integrierte Assertions zu ermöglichen. Für diese Zwecke wird ein abstraktes Datenmodell beschrieben werden. Das Assertion Interface soll die spezifikationsgetreue Modellintegration gewährleisten, sowie IC interne Assertionresultate dem umgebenen System über das Interface zugänglich machen und damit zum Debugging während der Laufzeit ermöglichen. Ferner werden die Codegenerierungs Templates erläutert und einBeispielsystem eingeführt, um die beschriebenden Konzepte zu validieren.Nowadays electronic systems design requires fast time to market and solid verification throughout the entire design flow. Many concepts have been researched to raise the level of abstraction during the design entry phase, whereas model-based design is the most promising one. Assertion-based verification enables the developer to specify properties of the design and to get report if these are violated. Assertions are common during development and simulation of electronic products but often are not included in the final silicon. In this thesis an UML-based model defined at Infineon Technologies for capturing design specification information and to generate code automatically using templates, will be extended to allow the description of an abstract debuggable assertion interface for silicon assertions. With help of the assertion interface it shall be possible to verify the correct module integration and to monitor IP-internal assertion checker results. Besides, the code-generation templates for the assertion interface model will be described. To demonstrate the usability of the developed concepts an example system will be introduced to validate the approach.Ilmenau, Techn. Univ., Diplomarbeit, 200

TwIRTee design exploration with Capella and IP-XAC

With the huge increase of embedded devices, model driven engineering becomes necesseray in order to cover a large spectrum of multiple abstraction levels. System models are exploited for design specification, system evaluation, verification and validation. Nowadays, no single modeling language and environment covers all these aspects. While Capella tool fits well to the most early stages of the development process, IP-XACT standard provides powerful capabilities to refine the design artifacts of the hardware point of view that appear during the latest phase of the design. While using different modeling languages for different purpose is perfectly acceptable in a development process, it is important to guarantee that information remains consistent across all models. This is why we build a formalized bridge between Capella and IP-XACT. In this paper, the transformation Capella /IP-XACT is described. The whole approach is illustrated by the design of TwIRTee – the robotic demonstrator of INGEQUIP – before concluding

Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design

International audienceModern SoC design may rely on models, or on highlevel description languages. Although very close, the benefits obtained from either sides can be substantially different (and mismatch may occur). The IP-Xact formalism, now a standard (IEEE 1685), was introduced to help assemble component IP from distinct sources into an integrated design. Components could be expressed in high-level HDLs such as SystemC, so should be the full design after translation. Experience shows that in fact this is hardly the case, specially in publicly available methods and tools. The present contribution goes one step into linking SystemC designs to their IP-Xact structural representation by translation. It then exports the resulting IP-Xact model into the UML/MARTE profile modeling framework, to allow to annotating existing models with additional information (again in a publicly available fashion, as opposed to vendor extensions). Even if our approach is still far from being complete, it bridges a number of gaps induce by the combined uses of SystemC and IP-Xact

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

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CubeSat Attitude Determination and Control System (ADACS) Characterization and Testing for Rendezvous and Proximity Operations (RPO)

This research endeavors to evaluate and characterize the performance of CubeSat specific commercial-off-the-shelf (COTS) Attitude Determination and Control Systems (ADACS) for Mission suitability. To ensure COTS components are capable of meeting CubeSat mission requirements, deliberate performance testing of critical CubeSat subsystems in flight-like conditions is essential. This effort focuses on testing the MAI-401 ADACS subsystem as configured to support the Grissom-1 CubeSat mission, as mounted to an air bearing, residing within a 3-axis Helmholtz Cage, and subjected to a simulated magnetic environment of various orbital parameters

Modeling and Simulation Methodologies for Digital Twin in Industry 4.0

The concept of Industry 4.0 represents an innovative vision of what will be the factory of the future. The principles of this new paradigm are based on interoperability and data exchange between dierent industrial equipment. In this context, Cyber- Physical Systems (CPSs) cover one of the main roles in this revolution. The combination of models and the integration of real data coming from the field allows to obtain the virtual copy of the real plant, also called Digital Twin. The entire factory can be seen as a set of CPSs and the resulting system is also called Cyber-Physical Production System (CPPS). This CPPS represents the Digital Twin of the factory with which it would be possible analyze the real factory. The interoperability between the real industrial equipment and the Digital Twin allows to make predictions concerning the quality of the products. More in details, these analyses are related to the variability of production quality, prediction of the maintenance cycle, the accurate estimation of energy consumption and other extra-functional properties of the system. Several tools [2] allow to model a production line, considering dierent aspects of the factory (i.e. geometrical properties, the information flows etc.) However, these simulators do not provide natively any solution for the design integration of CPSs, making impossible to have precise analysis concerning the real factory. Furthermore, for the best of our knowledge, there are no solution regarding a clear integration of data coming from real equipment into CPS models that composes the entire production line. In this context, the goal of this thesis aims to define an unified methodology to design and simulate the Digital Twin of a plant, integrating data coming from real equipment. In detail, the presented methodologies focus mainly on: integration of heterogeneous models in production line simulators; Integration of heterogeneous models with ad-hoc simulation strategies; Multi-level simulation approach of CPS and integration of real data coming from sensors into models. All the presented contributions produce an environment that allows to perform simulation of the plant based not only on synthetic data, but also on real data coming from equipments

Initial data sets for the Schwarzschild spacetime

A characterisation of initial data sets for the Schwarzschild spacetime is provided. This characterisation is obtained by performing a 3+1 decomposition of a certain invariant characterisation of the Schwarzschild spacetime given in terms of concomitants of the Weyl tensor. This procedure renders a set of necessary conditions --which can be written in terms of the electric and magnetic parts of the Weyl tensor and their concomitants-- for an initial data set to be a Schwarzschild initial data set. Our approach also provides a formula for a static Killing initial data set candidate --a KID candidate. Sufficient conditions for an initial data set to be a Schwarzschild initial data set are obtained by supplementing the necessary conditions with the requirement that the initial data set possesses a stationary Killing initial data set of the form given by our KID candidate. Thus, we obtain an algorithmic procedure of checking whether a given initial data set is Schwarzschildean or not.Comment: 16 page