The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm2/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×1012cm-2eV-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS

Monolithic integration of erbium-doped amplifiers with silicon-on-insulator waveguides

Monolithic integration of Al2O3:Er3+ amplifier technology with passive silicon-on-insulator waveguides is demonstrated. A signal enhancement of >7 dB at 1533 nm wavelength is obtained. The straightforward wafer-scale fabrication process, which includes reactive co-sputtering and subsequent reactive ion etching, allows for parallel integration of multiple amplifier and laser sections with silicon or other photonic circuits on a chip

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Demonstration of a heterogeneously integrated III-V/SOI single wavelength tunable laser

A heterogeneously integrated III-V-on-silicon laser is reported, integrating a III-V gain section, a silicon ring resonator for wavelength selection and two silicon Bragg grating reflectors as back and front mirrors. Single wavelength operation with a side mode suppression ratio higher than 45 dB is obtained. An output power up to 10 mW at 20 °C and a thermo-optic wavelength tuning range of 8 nm are achieved. The laser linewidth is found to be 1.7 MHz

Silicon optical modulators

Optical technology is poised to revolutionise short reach interconnects. The leading candidate technology is silicon photonics, and the workhorse of such interconnect is the optical modulator. Modulators have been improved dramatically in recent years. Most notably the bandwidth has increased from the MHz to the multi GHz regime in little more than half a decade. However, the demands of optical interconnect are significant, and many questions remain unanswered as to whether silicon can meet the required performance metrics. Minimising metrics such as the energy per bit, and device footprint, whilst maximising bandwidth and modulation depth are non trivial demands. All of this must be achieved with acceptable thermal tolerance and optical spectral width, using CMOS compatible fabrication processes. Here we discuss the techniques that have, and will, be used to implement silicon optical modulators, as well as the outlook for these devices, and the candidate solutions of the future

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15 mum ) dielectric layer that enables very low loss lines (~0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time