119,942 research outputs found
Fuzzy-logic-based control, filtering, and fault detection for networked systems: A Survey
This paper is concerned with the overview of the recent progress in fuzzy-logic-based filtering, control, and fault detection problems. First, the network technologies are introduced, the networked control systems are categorized from the aspects of fieldbuses and industrial Ethernets, the necessity of utilizing the fuzzy logic is justified, and the network-induced phenomena are discussed. Then, the fuzzy logic control strategies are reviewed in great detail. Special attention is given to the thorough examination on the latest results for fuzzy PID control, fuzzy adaptive control, and fuzzy tracking control problems. Furthermore, recent advances
on the fuzzy-logic-based filtering and fault detection problems are reviewed. Finally, conclusions are given and some possible future research directions are pointed out, for example, topics on two-dimensional networked systems, wireless networked control systems, Quality-of-Service (QoS) of networked systems, and fuzzy access control in open networked systems.This work was supported in part by the National Natural Science Foundation of China under Grants 61329301,
61374039, 61473163, and 61374127, the Hujiang Foundation of China under Grants C14002 andD15009, the Engineering and Physical Sciences Research Council (EPSRC) of the UK, the Royal Society of the UK, and the Alexander von Humboldt Foundation of Germany
Media Usage in Post-Secondary Education and Implications for Teaching and Learning
The Web 2.0 has permeated academic life. The use of online information
services in post-secondary education has led to dramatic changes in faculty
teaching methods as well as in the learning and study behavior of students. At
the same time, traditional information media, such as textbooks and printed
handouts, still form the basic pillars of teaching and learning. This paper
reports the results of a survey about media usage in teaching and learning
conducted with Western University students and instructors, highlighting trends
in the usage of new and traditional media in higher education by instructors
and students. In addition, the survey comprises part of an international
research program in which 20 universities from 10 countries are currently
participating. Further, the study will hopefully become a part of the ongoing
discussion of practices and policies that purport to advance the effective use
of media in teaching and learning
Distinguishing sequences for partially specified FSMs
Distinguishing Sequences (DSs) are used inmany Finite State Machine (FSM) based test techniques. Although Partially Specified FSMs (PSFSMs) generalise FSMs, the computational complexity of constructing Adaptive and Preset DSs (ADSs/PDSs) for PSFSMs has not been addressed. This paper shows that it is possible to check the existence of an ADS in polynomial time but the corresponding problem for PDSs is PSPACE-complete. We also report on the results of experiments with benchmarks and over 8 * 106 PSFSMs. © 2014 Springer International Publishing
Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding
Asynchronous circuits employing delay-insensitive codes for data
representation i.e. encoding and following a 4-phase return-to-zero protocol
for handshaking are generally robust. Depending upon whether a single
delay-insensitive code or multiple delay-insensitive code(s) are used for data
encoding, the encoding scheme is called homogeneous or heterogeneous
delay-insensitive data encoding. This article proposes a new latency optimized
early output asynchronous ripple carry adder (RCA) that utilizes single-bit
asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs)
which incorporate redundant logic and are based on the delay-insensitive
dual-rail code i.e. homogeneous data encoding, and follow a 4-phase
return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA),
and carry select adder (CSLA) designs, which are based on homogeneous or
heterogeneous delay-insensitive data encodings which correspond to the
weak-indication or the early output timing model, the proposed early output
asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is
found to result in reduced latency for a dual-operand addition operation. In
particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2
stages of SAFAs leads to reduced latency. The theoretical worst-case latencies
of the different asynchronous adders were calculated by taking into account the
typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is
made with their practical worst-case latencies estimated. The theoretical and
practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761
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