System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Technology sourcing by large incumbents through acquisition of small firms

Innovation activities in high technology industries provide considerable challenges for technology and innovation management. In particular, since these industries have a long history of radical innovations taking place through distinct industry cycles of higher and lower demand, firms frequently consider the option to use acquisitions as a means for technology sourcing. The paper investigates this behaviour for three high technology industries, namely semiconductor manufacturing, biotechnology and electronic design automation which is a specific sub-segment of the semiconductor industry. It analyses the association of firm characteristics with different aspects of acquisition behaviour with a particular focus being put on innovation-related firm characteristics. The paper confirms a substitutive relationship between acquisitions and own research activities as well as between own and acquired firm patenting, but also finds that firm size, financial conditions and geographical origin of the firm matter for acquisition behaviour.Acquisition, innovation, high technology, quantitative methods, research, R&D

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

Late Innovation Strategies in Asian Electronics Industries: A Conceptual Framework and Illustrative Evidence

This paper was published in Oxford Development Studies special issue in honor of the late Professor Linsu Kim. The paper reviews evidence on the evolution of electronics design in Asia's leading electronics exporting countries, to establish what capabilities have been developed, and to shed light on the forces that are driving "late innovation" strategies. It also reviews intellectual sources that can be used to theoretically ground these hypotheses. Using a well-known taxonomy of innovation that distinguishes incremental, modular, architectural and radical innovations, and the concept of "disruptive technologies", I argue that Asian firms may have realistic chances to engage in incremental innovations as well as in architectural innovations. However, to sustain "late innovation" strategies over a longer period, "complex system integration" capabilities are necessary to provide the missing link.

Innovation Offshoring:Asia's Emerging Role in Global Innovation Networks

Most analysts agree that critical ingredients for economic growth, competitiveness, and welfare in the United States have been policies that encourage strong investment in research and development (R&D) and innovation. In addition, there is a general perception that technological innovation must be based in the United States to remain a pillar of the American economy. Over the past decade, however, the rise of Asia as an important location for "innovation offshoring" has begun to challenge these familiar notions. Based on original research, this report demonstrates that innovation offshoring is driven by profound changes in corporate innovation management as well as by the globalization of markets for technology and knowledge workers. U.S. companies are at the forefront of this trend, but Asian governments and firms are playing an increasingly active role as promoters and new sources of innovation. Innovation offshoring has created a competitive challenge of historic proportions for the United States, requiring the nation to respond with a new national strategy. This report recommends that such a strategy include the following elements: output forecasting techniques ... Improve access to and collection of innovation-related data to inform the national policy debate; Address "home-made" causes of innovation offshoring by sustaining and building upon existing strengths of the U.S. innovation system; Support corporate innovation by (1) providing tax incentives to spur early-state investments in innovation start-ups and (2) reforming the U.S. patent system so it is more accessible to smaller inventors and innovators; and Upgrade the U.S. talent pool of knowledge workers by (1) providing incentives to study science and engineering, (2) encouraging the development of management, interpretive, cross-cultural, and other "soft" capabilities, and (3) encouraging immigration of highly skilled workers.Innovation Networks, Innovation Offshoring, Asia

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar