82 research outputs found
Circuit-Based Compact Model of Electron Spin Qubit
Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed
On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications
The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs
Design and implementation of 4 bit binary weighted current steering DAC
A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation
Lip Reading Deep Network Exploiting Multi-Modal Spiking Visual and Auditory Sensors
This work presents a lip reading deep neural network that fuses the asynchronous spiking outputs of two bio-inspired silicon multimodal sensors: the Dynamic Vision Sensor (DVS) and the Dynamic Audio Sensor (DAS). The fusion network is tested on the GRID visual-audio lipreading dataset. Classification is carried out using event-based features generated from the spikes of the DVS and DAS. Networks are trained separately on the two modalities and also jointly trained on both modalities. The jointly trained network when tested on DVS spike frames alone, showed a relative increase in accuracy of around 23% over that of the single DVS modality network
Complex Dynamics in Digital Nonlinear Oscillators: Experimental Analysis and Verification
A specific topology of Digital Nonlinear Oscillators (DNOs) has been implemented by using commercial off-the-shelf digital components to experimentally verify and demonstrate the capability of these circuits to support complex dynamics, independently from their implementation technology. In detail, a direct experimental evidence of the DNO dynamical behavior is presented at the analog level with a bifurcation diagram analysis, investigation of periodic and chaotic attractors, and dynamical stability. The autonomous circuit has been investigated as a source of entropy, adopting different figures of merit, including the Lempel–Ziv Complexity, to evaluate the dynamics measured under different operating conditions
Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications
With the advent of dedicated Deep Learning (DL) accelerators and neuromorphic
processors, new opportunities are emerging for applying deep and Spiking Neural
Network (SNN) algorithms to healthcare and biomedical applications at the edge.
This can facilitate the advancement of the medical Internet of Things (IoT)
systems and Point of Care (PoC) devices. In this paper, we provide a tutorial
describing how various technologies ranging from emerging memristive devices,
to established Field Programmable Gate Arrays (FPGAs), and mature Complementary
Metal Oxide Semiconductor (CMOS) technology can be used to develop efficient DL
accelerators to solve a wide variety of diagnostic, pattern recognition, and
signal processing problems in healthcare. Furthermore, we explore how spiking
neuromorphic processors can complement their DL counterparts for processing
biomedical signals. After providing the required background, we unify the
sparsely distributed research on neural network and neuromorphic hardware
implementations as applied to the healthcare domain. In addition, we benchmark
various hardware platforms by performing a biomedical electromyography (EMG)
signal processing task and drawing comparisons among them in terms of inference
delay and energy. Finally, we provide our analysis of the field and share a
perspective on the advantages, disadvantages, challenges, and opportunities
that different accelerators and neuromorphic processors introduce to healthcare
and biomedical domains. This paper can serve a large audience, ranging from
nanoelectronics researchers, to biomedical and healthcare practitioners in
grasping the fundamental interplay between hardware, algorithms, and clinical
adoption of these tools, as we shed light on the future of deep networks and
spiking neuromorphic processing systems as proponents for driving biomedical
circuits and systems forward.Comment: Submitted to IEEE Transactions on Biomedical Circuits and Systems (21
pages, 10 figures, 5 tables
Физически неклонируемые функции с управляемой задержкой распространения сигналов
Решается задача построения нового класса физически неклонируемых функций (ФНФ), обеспечивающих управление задержкой распространения сигнала через эле-менты, которые расположены на
пути его распространения. Актуальность такого исследования связана с активным развитием физической
криптографии. В работе преследуются следующие цели: построение базовых элементов ФНФ и их модификаций, разработка методики построения управляемых кольцевых осцилляторов на базе элементов
XOR и управляемых кольцевых осцилляторов, основанных на многовходовом переключении сигнала.
Методы. Используются методы синтеза и анализа цифровых устройств, в том числе на программируемых логических интегральных схемах, основы булевой алгебры и схемотехники
A simple bandgap reference based on VGO extraction with single-temperature trimming
Bandgap references are widely used in analog and mixed-signal systems to provide temperature-independent voltage or current reference. In traditional bandgap structure, the base-emitter voltage VBE of a diode is used to generate a complementary to absolute temperature (CTAT) voltage, which reduces as temperature increases. The base-emitter voltage difference ∆VBE between two diodes with the same current but different emitter areas supplies a proportional to absolute temperature (PTAT) voltage. With the proper adjustment of the coefficients of VBE and ∆VBE in a voltage summer, the temperature dependency of the summed voltage can be mostly canceled out and the output voltage can achieve a relative temperature-constant property. However, even though the linear terms of temperature-dependent components in PTAT and CTAT expressions can be canceled out, there are still some high order terms left, which still affect temperature dependency. For this reason, a first-order bandgap reference with only PTAT and CTAT linear term compensation cannot achieve a sufficiently low temperature coefficient (TC), normally ranging from 10ppm/°C to over 100ppm/°C. To achieve higher precision and lower TC, the high order terms also need to be considered and compensated by some techniques. This thesis study describes the development of a high order bandgap structure, including the initial thinking, design flow, equation derivation, circuit implementation, and simulation result
A CMOS Analog Front-End for Tunnelling Magnetoresistive Spintronic Sensing Systems
This paper presents a CMOS readout circuit for
an integrated and highly-sensitive tunnel-magnetoresistive
(TMR) sensor. Based on the characterization of the TMR sensor
in the finite-element simulation, using COMSOL Multiphysics,
the circuit including a Wheatstone bridge and an analogue
front-end (AFE) circuit, were designed to achieve low-noise and
low-power sensing. We present a transimpedance amplifier
(TIA) that biases and amplifies a TMR sensor array using
switched-capacitors external noise filtering and allows the
integration of TMR sensors on CMOS without decreasing the
measurement resolution. Designed using TSMC 0.18 μm 1V
technology, the amplifier consumes 160 nA at 1.8 V supply to
achieve a dc gain of 118 dB and a bandwidth of 3.8 MHz. The
results confirm that the full system is able to detect the magnetic
field in the pico-Tesla range with low circuit noise
(2.297 pA/√Hz) and low power consumption (86 μW). A
concurrent reduction in the power consumption and attenuation
of noise in TMR sensors makes them suitable for long-term
deployment in spintronic sensing systems
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