Electricity from photovoltaic solar cells: Flat-Plate Solar Array Project final report. Volume VI: Engineering sciences and reliability

The Flat-Plate Solar Array (FSA) Project, funded by the U.S. Government and managed by the Jet Propulsion Laboratory, was formed in 1975 to develop the module/array technology needed to attain widespread terrestrial use of photovoltaics by 1985. To accomplish this, the FSA Project established and managed an Industry, University, and Federal Government Team to perform the needed research and development. This volume of the series of final reports documenting the FSA Project deals with the Project's activities directed at developing the engineering technology base required to achieve modules that meet the functional, safety and reliability requirements of large-scale terrestrial photovoltaic systems applications. These activities included: (1) development of functional, safety, and reliability requirements for such applications; (2) development of the engineering analytical approaches, test techniques, and design solutions required to meet the requirements; (3) synthesis and procurement of candidate designs for test and evaluation; and (4) performance of extensive testing, evaluation, and failure analysis to define design shortfalls and, thus, areas requiring additional research and development. During the life of the FSA Project, these activities were known by and included a variety of evolving organizational titles: Design and Test, Large-Scale Procurements, Engineering, Engineering Sciences, Operations, Module Performance and Failure Analysis, and at the end of the Project, Reliability and Engineering Sciences. This volume provides both a summary of the approach and technical outcome of these activities and provides a complete Bibliography (Appendix A) of the published documentation covering the detailed accomplishments and technologies developed

The predictive functional control and the management of constraints in GUANAY II autonomous underwater vehicle actuators

Autonomous underwater vehicle control has been a topic of research in the last decades. The challenges addressed vary depending on each research group's interests. In this paper, we focus on the predictive functional control (PFC), which is a control strategy that is easy to understand, install, tune, and optimize. PFC is being developed and applied in industrial applications, such as distillation, reactors, and furnaces. This paper presents the rst application of the PFC in autonomous underwater vehicles, as well as the simulation results of PFC, fuzzy, and gain scheduling controllers. Through simulations and navigation tests at sea, which successfully validate the performance of PFC strategy in motion control of autonomous underwater vehicles, PFC performance is compared with other control techniques such as fuzzy and gain scheduling control. The experimental tests presented here offer effective results concerning control objectives in high and intermediate levels of control. In high-level point, stabilization and path following scenarios are proven. In the intermediate levels, the results show that position and speed behaviors are improved using the PFC controller, which offers the smoothest behavior. The simulation depicting predictive functional control was the most effective regarding constraints management and control rate change in the Guanay II underwater vehicle actuator. The industry has not embraced the development of control theories for industrial systems because of the high investment in experts required to implement each technique successfully. However, this paper on the functional predictive control strategy evidences its easy implementation in several applications, making it a viable option for the industry given the short time needed to learn, implement, and operate, decreasing impact on the business and increasing immediacy.Peer ReviewedPostprint (author's final draft

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Exploiting smallest error to calibrate non-linearity in SAR ADCs

This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part