On real time optical wireless communication channel emulator design with FPGAs

This paper discusses the implementation details of a channel emulator suited for optical wireless communications (OWC) systems. The channel emulator comprises functional blocks able to model the transmitter, the receiver and the channel. It is in this sense a valuable tool for system performance evaluation. The proposed design uses field programmable gate arrays (FPGAs) as supporting hardware platform, enabling flexible and expedite interconnection with other system blocks. The achieved design operates in real time, allowing timely and realistic assessment of the channel and terminal equipment impairments on the overall system. Achieved results demonstrate the feasibility to address channel emulation with 500ps time resolution, with negligible quantization errors when compared to the predefined channel coefficients.publishe

A contribution to the monitoring of ceramic surface quality using a low-cost piezoelectric transducer in the grinding operation

The grinding process is usually one of the last stages in the manufacturing process chain since it can provide superior surface finish and closer dimensional tolerances. However, due to peculiarities of the grinding process, a workpiece material is susceptible to many problems, and demands a reliable real-time monitoring system. Some grinding monitoring systems have been proposed by means of sensors. However, the literature is still scarce in terms of employing time–frequency analysis techniques during the grinding of ceramics. Thus, this paper proposes an application of a low-cost piezoelectric transducer (PZT) in the analysis of the surface quality of ceramic workpieces during the grinding process by means of the frequency–time domain technique along with the ratio of power (ROP) parameter. An integrated, high-cost, commonly-used acoustic emission (AE) sensor was employed in order to compare the results with the low-cost PZT transducer. Tests were performed using a surface grinding machine. Three depth of cut values were selected in order to represent slight, moderate, and severe grinding conditions. Signals were collected at 2 MHz. The short-time Fourier transform (STFT) was studied in order to obtain the frequency variations over time. An analysis of the ROP values was performed in order to establish a correlation with the surface roughness. The ROP values are highly desirable for setting a threshold to detect the workpiece surface quality and for implementing it into a monitoring system. The results using the PZT transducer showed a great similarity to those obtained using the AE sensor

Measurements for non-intrusive load monitoring through machine learning approaches

The topic of non-intrusive load monitoring (NILM) has seen a significant increase in research interest over the past decade, which has led to a significant increase in the performance of these systems. Nowadays, NILM systems are used in numerous applications, in particular by energy companies that provide users with an advanced management service of different consumption. These systems are mainly based on artificial intelligence algorithms that allow the disaggregation of energy by processing the absorbed power signal over more or less long time intervals (generally from fractions of an hour up to 24 h). Less attention was paid to the search for solutions that allow non-intrusive monitoring of the load in (almost) real time, that is, systems that make it possible to determine the variations in loads in extremely short times (seconds or fractions of a second). This paper proposes possible approaches for non-intrusive load monitoring systems operating in real time, analysing them from the point of view of measurement. The measurement and post-processing techniques used are illustrated and the results discussed. In addition, the work discusses the use of the results obtained to train machine learning algorithms that allow you to convert the measurement results into useful information for the user

High-Gain Metasurface in Polyimide On-Chip Antenna Based on CRLH-TL for Sub-Terahertz Integrated Circuits

This paper presents a novel on-chip antenna using standard CMOS-technology based on metasurface implemented on two-layers polyimide substrates with a thickness of 500μm. The aluminium ground-plane with thickness of 3μm is sandwiched between the two-layers. Concentric dielectric-rings are etched in the ground-plane under the radiation patches implemented on the top-layer. The radiation patches comprise concentric metal-rings that are arranged in a 3×3 matrix. The antennas are excited by coupling electromagnetic energy through the gaps of the concentric dielectric-rings in the ground-plane using a microstrip feedline created on the bottom polyimide-layer. The open-ended feedline is split in three-branches that are aligned under the radiation elements to couple the maximum energy. In this structure, the concentric metal-rings essentially act as series left-handed capacitances CL that extend the effective aperture area of the antenna without affecting its dimensions, and the concentric dielectric rings etched in the ground-plane act as shunt left-handed inductors LL, which suppress the surface-waves and reduce the substrates losses that leads to improved bandwidth and radiation properties. The overall structure behaves like a metasurface that is shown to exhibit a very large bandwidth of 0.350-0.385THz with an average radiation gain and efficiency of 8.15dBi and 65.71%, respectively. It has dimensions of 6×6×1mm3 that makes it suitable for on-chip implementation

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations' performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication. The proposed architecture is fully scalable with the maximum matrix dimension limited by the available resources. In addition, a design environment is also developed, permitting assistance, through a friendly interface, from the customization of the hardware computing unit to the generation of the final synthesizable IP core. For N x N matrices, the architecture requires N ALU-RAM blocks and performs O(N*N), requiring N*N +7 and N +7 clock cycles for matrix-matrix and matrix-vector operations, respectively. For the tested Virtex7 FPGA device, the computation for 500 x 500 matrices allows a maximum clock frequency of 346 MHz, achieving an overall performance of 173 GOPS. This architecture shows higher performance than other state-of-the-art matrix computing units

A Study of the Sensitivity of Energy Conversion Efficiency to Load Variation in Class-E Resonant Power Inverter

In this thesis the sensitivity of energy conversion efficiency (ECE) and output power of a class-E resonant inverter under variable resistive and inductive load assignments is examined for wireless power transfer (WPT) applications. By performing simulation and mathematical analysis, it was found that the on-resistance of the switching device has minor effect on the design’s efficiency. Additional comparisons between the simulation and mathematical analysis show reasonable output power and ECE load variation performance for the design, but with unique load impedances where zero voltage switching (ZVS) and zero derivative switching (ZDS) are achieved. These comparisons also expose inaccurate mathematical assumptions. Experimental test results are presented to validate simulation and mathematical assumptions. These tests also show invalid assumptions used in the simulation and mathematical analysis and the performance of the class-E resonant power inverter suffer due to the difference in resonant frequencies during switch on and off state periods, nonlinear shunt capacitance, and parasitic impedances

A Novel Block-based Watermarking Scheme Using the SVD Transform

In this paper, a block-based watermarking scheme based on the Singular Value Decomposition (SVD) is proposed. Our watermark, a pseudo-random Gaussian sequence, is embedded by modifying the angles formed by the right singular vectors of each block of the original image. The orthogonality property of the right singular vector matrix is preserved during the embedding process. Several experiments have been carried out to test the performance of the proposed scheme against different attack scenarios. We conclude that the proposed scheme is resistant against common signal processing operations and attacks, while it preserves the quality of the original image