43 research outputs found
A design for testability study on a high performance automatic gain control circuit.
A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente
An efficient logic fault diagnosis framework based on effect-cause approach
Fault diagnosis plays an important role in improving the circuit design process and the
manufacturing yield. With the increasing number of gates in modern circuits, determining
the source of failure in a defective circuit is becoming more and more challenging.
In this research, we present an efficient effect-cause diagnosis framework for
combinational VLSI circuits. The framework consists of three stages to obtain an accurate
and reasonably precise diagnosis. First, an improved critical path tracing algorithm is
proposed to identify an initial suspect list by backtracing from faulty primary outputs
toward primary inputs. Compared to the traditional critical path tracing approach, our
algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to
rank the suspects so that the most suspicious one will be ranked at or near the top. Several
fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis,
fault simulation is performed on the top suspect nets using several common fault models.
The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this
diagnosis approach is efficient both in terms of memory space and CPU time and the
diagnosis results are accurate and reasonably precise
Voltage sensing based built-in current sensor for IDDQ test
Quiescent current leakage test of the VDD supply (IDDQ Test) has been proven an
effective way to screen out defective chips in manufacturing of Integrated Circuits (IC).
As technology advances, the traditional IDDQ test is facing more and more challenges. In
this research, a practical built-in current sensor (BICS) is proposed and the design is
verified by three generations of test chips. The BICS detects the signal by sensing the
voltage drop on supply lines of the circuit under test (CUT). Then the sensor performs
analog-to-digital conversion of the input signal using a stochastic process with scan chain
readout. Self-calibration and digital chopping are used to minimize offset and low
frequency noise and drift. This non-invasive procedure avoids any performance
degradation of the CUT. The measurement results of test chips are presented. The sensor
achieves a high IDDQ resolution with small chip area overhead. This will enable IDDQ of
future technology generations
Investigation into voltage and process variation-aware manufacturing test
Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation
A Behavioral Model of a Built-in Current Sensor for IDDQ Testing
IDDQ testing is one of the most effective methods for detecting defects in integrated
circuits. Higher leakage currents in more advanced semiconductor technologies have
reduced the resolution of IDDQ test. One solution is to use built-in current sensors. Several
sensor techniques for measuring the current based on the magnetic field or voltage drop
across the supply line have been proposed. In this work, we develop a behavioral model
for a built-in current sensor measuring voltage drop and use this model to better
understand sensor operation, identify the effect of different parameters on sensor
resolution, and suggest design modifications to improve future sensor performance
Test Cost Reduction for Logic Circuits——Reduction of Test Data Volume and Test Application Time——
論理回路の大規模化とともに,テストコストの増大が深刻な問題となっている.特に大規模な論理回路では,テストデータ量やテスト実行時間の削減が,テストコスト削減の重要な課題である.本論文では,高い故障検出率のテストパターンをできるだけ少ないテストベクトル数で実現するためのテストコンパクション技術,付加ハードウェアによるテストデータの展開・伸長を前提に圧縮を行うテストコンプレッション技術,及び,スキャン設計回路におけるテスト実行時間削減技術について概説する
Development of a CMOS IDDq Testing Environment
A majority of defects found in CMOS technology display elevated quiescent current magnitudes but still may pass functionality tests. By monitoring this power supply current, defect coverage can be elevated past the traditional stuck-at-fault coverage. This study provides a test methodology centered around current supply monitoring. By analyzing fabrication data, defect models, built-in current sensors, current and delay estimation, test set generation, and the QTAG standard, a technique is developed for CMOS integrated circuit testing. A built-in current sensor is presented, which through simulation, exhibits fast detection time. Novel techniques to enhance this time are also presented
Learning digital test and diagnostics via Internet
An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the hardware equipments, which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exams. The tools support university courses on digital electronics, computer hardware, testing and design for testability to learn by hands-on exercises how to design digital systems, how to make them testable, how to build self-testing systems, how to generate test patterns, how to analyze the quality of tests, and how to localize faults in hardware. The tasks chosen for hands-on training represent simultaneously research problems, which allow to fostering in students critical thinking, problem solving skills and creativity
Integrated circuit outlier identification by multiple parameter correlation
Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed