27 research outputs found
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
Lithography is fundamental to integrated circuit fabrication, necessitating
large computation overhead. The advancement of machine learning (ML)-based
lithography models alleviates the trade-offs between manufacturing process
expense and capability. However, all previous methods regard the lithography
system as an image-to-image black box mapping, utilizing network parameters to
learn by rote mappings from massive mask-to-aerial or mask-to-resist image
pairs, resulting in poor generalization capability. In this paper, we propose a
new ML-based paradigm disassembling the rigorous lithographic model into
non-parametric mask operations and learned optical kernels containing
determinant source, pupil, and lithography information. By optimizing
complex-valued neural fields to perform optical kernel regression from
coordinates, our method can accurately restore lithography system using a
small-scale training dataset with fewer parameters, demonstrating superior
generalization capability as well. Experiments show that our framework can use
31% of parameters while achieving 69 smaller mean squared error with
1.3 higher throughput than the state-of-the-art.Comment: Accepted by DAC2
MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning
Placement is an essential task in modern chip design, aiming at placing
millions of circuit modules on a 2D chip canvas. Unlike the human-centric
solution, which requires months of intense effort by hardware engineers to
produce a layout to minimize delay and energy consumption, deep reinforcement
learning has become an emerging autonomous tool. However, the learning-centric
method is still in its early stage, impeded by a massive design space of size
ten to the order of a few thousand. This work presents MaskPlace to
automatically generate a valid chip layout design within a few hours, whose
performance can be superior or comparable to recent advanced approaches. It has
several appealing benefits that prior arts do not have. Firstly, MaskPlace
recasts placement as a problem of learning pixel-level visual representation to
comprehensively describe millions of modules on a chip, enabling placement in a
high-resolution canvas and a large action space. It outperforms recent methods
that represent a chip as a hypergraph. Secondly, it enables training the policy
network by an intuitive reward function with dense reward, rather than a
complicated reward function with sparse reward from previous methods. Thirdly,
extensive experiments on many public benchmarks show that MaskPlace outperforms
existing RL approaches in all key performance metrics, including wirelength,
congestion, and density. For example, it achieves 60%-90% wirelength reduction
and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip
layout design. The deliverables are released at
https://laiyao1.github.io/maskplace
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Improved Physical Design for Manufacturing Awareness and Advanced VLSI
Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research