IC immunity modeling process validation using on-chip measurements

International audienceDeveloping integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process

Measurement and Analysis of Electromagnetic Field, Noise and IC Logic Error due to system-level ESD

Department of Electrical EngineeringAs the high performance very-large-scale integration (VLSI) systems operate with high speed and low voltage, the system-level electrostatic discharge (ESD) event is becoming one of the important noise sources causing logic errors and system malfunctions such as system reboot or fault. To understand the ESD noise phenomena and improve the system-level ESD noise immunity for devices, the accurate ESD noise measurement and analysis of IC logic errors are necessary. Section I is written for the tendency of ESD research and previous research. This paper presents the noise type correlation by measuring the signal-ground noise and power-ground noise simultaneously on the fundamental F/F operation circuit and shows the type of error from chip, in section II. Furthermore, the decoupling capacitors (de-cap) effect that can reduce the error occurrence by checking the error rate are analyzed. A generator is designed on the main board which is based on real operating laptop, and the chip on dual in-line memory module (DIMM) is also designed to perform the basic F/F operation. The clock and data input from generator are connected to the chip on the DIMM through the small outline dual in-line memory module (SODIMM) socket. ESD occurs at the corner of the ground plane of main board. The specification of the ESD generator satisfies IEC 61000-4-2 [1]. The ESD current flows along the ground strap, and affects the DIMM. IN-ground, CLK-ground, OUT-ground and power-ground on the DIMM are simultaneously measured to determine the effect of ESD on the main board. To analyze the error ratio according to the ESD voltage level, the voltage setup of the ESD gun is 3kV, 5kV and 8kV. To investigate the effects of chip shielding and DIMM de-caps on the error probability of DIMM, the experiment is conducted under the several conditions. After confirming the normal operation for each condition, the error type on the DIMM due to the ESD occurred in the circuit is analyzed and the statistics are shown. The results are verified by H-spice simulation, Vector Network Analyzer (VNA) and HFSS simulation. In order to obtain the improvement method of the DIMM immunity, experiments are conducted to find out the effective position and number of DIMM de-cap. Accurate measurements of electromagnetic fields are also essential to analyze the radiated noise due to unwanted electrostatic discharge (ESD) events at electronic devices. Usually, to know the radiated noise by ESD events, the voltages induced at field probes are measured, and the fields are obtained from the voltage by de-convolving the probe factor. In section ???, the two probe-factor deconvolution methods are investigated and compared in the measurements of the fields induced by system-level ESD events.ope

The conducted immunity of SPI EEPROM memories

International audienceThis paper focus on the conducted immunity measurement of non-volatile memories up to 1 GHz. A specific measurement flow is introduced, which makes possible to compare the EMC performances in different test cases. Trough measurements and simulation, this study gives a real view on the immunity difference of this integrated circuits (IC)

On-die transient event sensors and system-level ESD testing

System level electrostatic discharge (ESD) testing of electronic products is a critical part of product certification. Test methods were investigated to develop system level ESD simulation models to predict soft-failures in a system with multiple sensors. These methods rely completely on measurements. The model developed was valid only for the linear operation range of devices within the system. These methods were applied to a commercial product and used to rapidly determine when a soft failure would occur. Attaching cables and probes to determine stress voltages and currents within a system, as in the previous study, is time-consuming and can alter the test results. On-chip sensors have been developed which allow the user to avoid using cables and probes and can detect an event along with the level, polarity, and location of a transient event seen at the I/O pad. The sensors were implemented with minimum area consumption and can be implemented within the spacer cell of an I/O pad. Some of the proposed sensors were implemented in a commercial test microcontroller and have been tested to successfully record the event occurrence, location, level, and polarity on that test microcontroller. System level tests were then performed on a pseudo-wearable device using the on-chip sensors. The measurements were successful in capturing the peak disturbance and counting the number of ESD events without the addition of any external measurement equipment. A modification of the sensors was also designed to measure the peak voltage on a trace or pin inside a complex electronic product. The peak current can also be found when the sensor is placed across a transient voltage suppressor with a known I-V curve. The peak level is transmitted wirelessly to a receiver outside the system using frequency-modulated magnetic or electric fields, thus allowing multiple measurements to be made without opening the enclosure or otherwise modifying the system. Simulations demonstrate the sensors can accurately detect the peak transient voltage and transmit the level to an external receiver --Abstract, page iv

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

Assessment of the Immunity of Unshielded Multicore Integrated Circuits to Near Field Injection

International audienceThis paper presents a comparative assessment of the electromagnetic immunity of 4 integrated logic cores to near-field injection. These cores, located on the same die, are identical from a functional point of view, but differ by their design strategies. The injection is performed above each core according to the 6 components of the electromagnetic field, using appropriate probes. These results demonstrate that the die and bondwires of an integrated circuit can be sensitive to both magnetic and electric fields, and that some design rules can improve the immunity of integrated circuits to near-field interference

TVS transient behavior modeling method, and system-level effective ESD design for USB3.x interface

This research proposal presents a methodology whereby a protection device can be modeled in SPICE compatible platforms with respect to the transient behaviors during Electrostatic Discharge (ESD) events. This methodology uses an exclusively black-box approach to characterize the parameters of the protection device, thereby allowing it to be implemented without intimate knowledge of the DUT. Results of this methodology can be used to predict the transient response (conductivity modulation and snapback delay) of the ESD protection devices, and thereby predicts how much current could flow into the device (typically a digital IO pin) under protection. The transient behavior modeling methodology for the ESD protection device is developed for the purpose of system level ESD design, and it is part of the study of System-level Effective ESD Design (SEED) methodology. During the work, the transient behavior modeling method and the SEED methodology have been applied to a high-speed USB3.x repeater IC circuit design. This article introduces a PCB test board working as USB3.x repeater, which allows to place various on-board protection devices and to measure the residual voltage and current at the IO pin accurately. In Section 2, the transient behavior modeling framework and the characterization method will be introduced. The validation results of three different types of protection devices are shown in the end of the section. In Section 3, the implementation of SEED methodology to a USB3.x system design will be introduced. The measurement setup is described in detail. Finally, the validation results for different scenarios will be shown --Abstract, page iii