A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

Network-on-Chips (NoCs) have emerged as a communication infrastructure for the multi-core System-on-Chips (SoCs). Despite its advantages, due to the multi-hop communication over the metal interconnects, traditional Mesh based NoC architectures are not scalable in terms of performance and energy consumption. Folded architectures such as Torus and Folded Torus were proposed to improve the performance of NoCs while retaining the regular tile-based structure for ease of manufacturing. Ultra-low-latency and low-power express channels between communicating cores have also been proposed to improve the performance of conventional NoCs. However, the performance gain of these approaches is limited due to metal/dielectric based interconnection. Many emerging interconnect technologies such as 3D integration, photonic, Radio Frequency (RF), and wireless interconnects have been envisioned to alleviate the issues of a metal/dielectric interconnect system. However, photonic and RF interconnects need the additional physically overlaid optical waveguides or micro-strip transmission lines to enable data transmission across the NoC. Several on-chip antennas have shown to improve energy efficiency and bandwidth of on-chip data communications. However, the date rates of the mm-wave wireless channels are limited by the state-of-the-art power-efficient transceiver design. Recent research has brought to light novel graphene based antennas operating at THz frequencies. Due to the higher operating frequencies compared to mm-wave transceivers, the data rate that can be supported by these antennas are significantly higher. Higher operating frequencies imply that graphene based antennas are just hundred micrometers in size compared to dimensions in the range of a millimeter of mm-wave antennas. Such reduced dimensions are suitable for integration of several such transceivers in a single NoC for relatively low overheads. In this work, to exploit the benefits of a regular NoC structure in conjunction with emerging Graphene-based wireless interconnect. We propose a toroidal folding based NoC architecture. The novelty of this folding based approach is that we are using low power, high bandwidth, single hop direct point to point wireless links instead of multihop communication that happens through metallic wires. We also propose a novel phased based communication protocol through which multiple wireless links can be made active at a time without having any interference among the transceiver. This offers huge gain in terms of performance as compared to token based mechanism where only a single wireless link can be made active at a time. We also propose to extend Graphene-based wireless links to enable energy-efficient, phase-based chip-to-chip communication to create a seamless, wireless interconnection fabric for multichip systems as well. Through cycle-accurate system-level simulations, we demonstrate that such designs with torus like folding based on THz links instead of global wires along with the proposed phase based multichip systems. We provide estimates that they are able to provide significant gains (about 3 to 4 times better in terms of achievable bandwidth, packet latency and average packet energy when compared to wired system) in performance and energy efficiency in data transfer in a NoC as well as multichip system. Thus, realization of these kind of interconnection framework that could support high data rate links in Tera-bits-per-second that will alleviate the capacity limitations of current interconnection framework

Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Reliability-aware multi-segmented bus architecture for photonic networks-on-chip

Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared to traditional on-chip buses. However, the multi-hop wireline paths in traditional NoCs result in high latency and energy dissipation causing an overall degradation in performance, especially for increasing system size. To alleviate this problem a few radically different interconnect technologies are envisioned. One such method of interconnecting different cores in NoCs is photonic interconnects. Photonic NoCs are on-chip communications networks in which information is transmitted in the form of optical signals. Photonic interconnection is one of the leading examples of emerging technology for on-chip interconnects. Existing innovative photonic NoC architectures have improved performance and reduced energy dissipation. Most architectures use Wavelength Division Multiplexing (WDM) on the photonic waveguides to increase the data bandwidth. However they have issues relating to reliability, such as waveguide losses and adjacent channel crosstalk. These phenomena could have a crippling effect on a system, and most current architectures do not address these effects. A newly proposed topology, known as the Multiple-Segmented Bus topology, or MSB, has shown promise for solving, or at least reducing, many of the problems plaguing the design of photonic networks using a modification of a folded torus to transmit different wavelength signals simultaneously. The MSB segments the waveguides into smaller parts to limit the waveguide losses. The formal performance evaluation of this proposed architecture has not been completed. This thesis will analyze the performance of such a network when implemented as a NoC in terms of data bandwidth, energy dissipation, latency, and reliability. By analyzing and comparing performance, energy dissipations, and reliability, the MSB-based photonic NoC (MSB-PNoC) can be compared to other state-of-the-art photonic NoCs to determine the feasibility of this topology for future network-on-chip designs