Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity

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The world is heading towards the IoE (Internet of Everything) where everything will be connected to each other. New flexible, light-weight and low-cost electronic devices are needed to add intelligence everywhere in our surroundings. Conventional silicon-based manufacturing is not the best solution because silicon is mechanically rigid and expensive. One way to manufacture these devices cost-effectively in a very large scale is by roll-to-roll screen printing on flexible substrates. However, due to the low calculation performance of current printed electronics, silicon ICs are still needed to act as brains of the devices. Many studies about chip-on-flex or chip-on-film (COF) attachments are available but information about the integration of a silicon chip directly on a screen printed substrate is needed. This thesis investigates bare chip attachment on printed flexible circuitry and evaluates its subsequent level of bendability. The chip was attached on the high-density rotary screen printed circuitry using a flip-chip technique with anisotropic conductive adhesives (ACP and ACF). A selection of chips was stud bumped with gold. Chips without bumps were more challenging to bond due to the surface roughness of the screen printed lines and a small marginal of the suitable bonding pressure. A chip should be exactly parallel with the substrate while bonding so that the pressure is correct on all pads. After finding the suitable bonding parameters, approximately 90 % of the ACP bonded and 96 % of the ACF bonded interconnections worked without bumps. Stud bumping increased the yield almost to 100 % and decreased the contact resistances approximately 75% making the contacts more reliable. Calendering was tested for printed lines to increase their uniformity and decrease the pad height deviation by heating and pressing them with high force. Calendering reduced the line heights by approximately 1 μm and decreased the surface roughness, but following this process there still existed at least a 2 μm variation in the line heights (nominal line height 5 μm). Bending reliability of the chip attachments on flexible plastic substrates was determined using a self-built bending test set-up which bends the sample between two rigid plates. All chip attachments studied withstood at least a 2.5 cm bending radius. The main results of this thesis were to demonstrate bare die integration on screen printed circuitry and to show its suitability for flexible hybrid electronic applications. Still further development of the bonding process and materials are needed to achieve more reliable long-term solutions

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems