Data compression techniques applied to high resolution high frame rate video technology

An investigation is presented of video data compression applied to microgravity space experiments using High Resolution High Frame Rate Video Technology (HHVT). An extensive survey of methods of video data compression, described in the open literature, was conducted. The survey examines compression methods employing digital computing. The results of the survey are presented. They include a description of each method and assessment of image degradation and video data parameters. An assessment is made of present and near term future technology for implementation of video data compression in high speed imaging system. Results of the assessment are discussed and summarized. The results of a study of a baseline HHVT video system, and approaches for implementation of video data compression, are presented. Case studies of three microgravity experiments are presented and specific compression techniques and implementations are recommended

Study on high Performance and Effective Watermarking Scheme using Hybrid Transform (DCT-DWT)

Nowadays healthcare infrastructure depends on Hospital Information Systems (HIS), Radiology Information Systems (RIS),Picture archiving and Communication Systems (PACS) as these provide new ways to store, access and distribute medical data . It eliminates the security risk. Conversely, these developments have introduced new risks for unsuitable deployment of medical information flowing in open networks, provided the effortlessness with which digital content can be manipulated. It is renowned that the integrity and confidentiality of medical data is a serious topic for ethical and legal reasons. Medical images need to be kept intact in any condition and prior to any operation as well need to be checked for integrity and verification. Watermarking is a budding technology that is capable of assisting this aim. In recent times, frequency domain watermarking algorithms have gained immense importance due to their widespread use. Subsequently, the watermark embedding and extraction are performed in frequency domain using the presented scheme. The proposed watermarking scheme, the watermark extraction compared with the original image for calculating SSIM.The effectiveness of the proposed watermarking scheme is demonstrated with the aid of experimental results

Novel sparse OBC based distributed arithmetic architecture for matrix transforms

Inner product (IP) forms the basis of a number of signal processing algorithms and applications such as transforms, filters, communication systems etc. Distributed arithmetic (DA) provides an effective methodology to implement IP of vectors and matrices using a simple combination of memory elements, adders and shifters instead of lumped multipliers. This bit level rearrangement results in much higher computational efficiencies and yields compact designs highly suited for high performance resource constrained applications. Offset binary coding (OBC) is an effective technique to further optimize the DA, and allows us to reduce the memory requirements by a factor of two, with minimum additional computational complexity. This makes OBC-DA attractive for applications that are both resource and memory constrained. In addition, sparse matrix factorization techniques can be exploited to further reduce the size of the DA-ROMs. In this paper, the design and implementation of a novel OBC based DA is demonstrated using a generic architecture for implementing discrete orthogonal transforms (DOTs). Implementation is performed on the Xilinx Virtex-II Pro field programmable gate array (FPGA), and a detailed comparison between conventional and OBC based DA is presented to highlight the trade offs in various design metrics including performance, area and power

Mengenal pasti tahap pengetahuan pelajar tahun akhir Ijazah Sarjana Muda Kejuruteraan di KUiTTHO dalam bidang keusahawanan dari aspek pengurusan modal

Malaysia ialah sebuah negara membangun di dunia. Dalam proses pembangunan ini, hasrat negara untuk melahirkan bakal usahawan beijaya tidak boleh dipandang ringan. Oleh itu, pengetahuan dalam bidang keusahawanan perlu diberi perhatian dengan sewajarnya; antara aspek utama dalam keusahawanan ialah modal. Pengurusan modal yang tidak cekap menjadi punca utama kegagalan usahawan. Menyedari hakikat ini, kajian berkaitan Pengurusan Modal dijalankan ke atas 100 orang pelajar Tahun Akhir Kejuruteraan di KUiTTHO. Sampel ini dipilih kerana pelajar-pelajar ini akan menempuhi alam pekeijaan di mana mereka boleh memilih keusahawanan sebagai satu keijaya. Walau pun mereka bukanlah pelajar dari jurusan perniagaan, namun mereka mempunyai kemahiran dalam mereka cipta produk yang boleh dikomersialkan. Hasil dapatan kajian membuktikan bahawa pelajar-pelajar ini berminat dalam bidang keusahawanan namun masih kurang pengetahuan tentang pengurusan modal terutamanya dalam menentukan modal permulaan, pengurusan modal keija dan caracara menentukan pembiayaan kewangan menggunakan kaedah jualan harian. Oleh itu, satu garis panduan Pengurusan Modal dibina untuk memberi pendedahan kepada mereka

FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique

The real time fingerprint biometric system is implemented using FGPA. In this paper, we propose FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique with novel adaptive threshold for each person. The fingerprint images are considered from FVC2004 (DB3_A) and processed to resize fingerprint size to 256x256. The DWT is applied on fingerprint and considered only LL coefficients as features of fingerprint. The Adaptive Threshold value for each person is computed using Deviations between two successive samples of a person, Average Deviation, Standard Deviation and constant. The Adaptive Threshold for test image is computed using Deviations between test images and samples of database, Average Deviation, Standard Deviation and constant. If the Average Threshold of test image is less than Average Threshold of a person then it is considered as match else mismatched. It is observed that the success rate of identifying a person is high in the proposed method compared to existing techniques and also the device utilization in the proposed architecture is less compared to existing architecture

Lossless and low-cost integer-based lifting wavelet transform

Discrete wavelet transform (DWT) is a powerful tool for analyzing real-time signals, including aperiodic, irregular, noisy, and transient data, because of its capability to explore signals in both the frequency- and time-domain in different resolutions. For this reason, they are used extensively in a wide number of applications in image and signal processing. Despite the wide usage, the implementation of the wavelet transform is usually lossy or computationally complex, and it requires expensive hardware. However, in many applications, such as medical diagnosis, reversible data-hiding, and critical satellite data, lossless implementation of the wavelet transform is desirable. It is also important to have more hardware-friendly implementations due to its recent inclusion in signal processing modules in system-on-chips (SoCs). To address the need, this research work provides a generalized implementation of a wavelet transform using an integer-based lifting method to produce lossless and low-cost architecture while maintaining the performance close to the original wavelets. In order to achieve a general implementation method for all orthogonal and biorthogonal wavelets, the Daubechies wavelet family has been utilized at first since it is one of the most widely used wavelets and based on a systematic method of construction of compact support orthogonal wavelets. Though the first two phases of this work are for Daubechies wavelets, they can be generalized in order to apply to other wavelets as well. Subsequently, some techniques used in the primary works have been adopted and the critical issues for achieving general lossless implementation have solved to propose a general lossless method. The research work presented here can be divided into several phases. In the first phase, low-cost architectures of the Daubechies-4 (D4) and Daubechies-6 (D6) wavelets have been derived by applying the integer-polynomial mapping. A lifting architecture has been used which reduces the cost by a half compared to the conventional convolution-based approach. The application of integer-polynomial mapping (IPM) of the polynomial filter coefficient with a floating-point value further decreases the complexity and reduces the loss in signal reconstruction. Also, the “resource sharing” between lifting steps results in a further reduction in implementation costs and near-lossless data reconstruction. In the second phase, a completely lossless or error-free architecture has been proposed for the Daubechies-8 (D8) wavelet. Several lifting variants have been derived for the same wavelet, the integer mapping has been applied, and the best variant is determined in terms of performance, using entropy and transform coding gain. Then a theory has been derived regarding the impact of scaling steps on the transform coding gain (GT). The approach results in the lowest cost lossless architecture of the D8 in the literature, to the best of our knowledge. The proposed approach may be applied to other orthogonal wavelets, including biorthogonal ones to achieve higher performance. In the final phase, a general algorithm has been proposed to implement the original filter coefficients expressed by a polyphase matrix into a more efficient lifting structure. This is done by using modified factorization, so that the factorized polyphase matrix does not include the lossy scaling step like the conventional lifting method. This general technique has been applied on some widely used orthogonal and biorthogonal wavelets and its advantages have been discussed. Since the discrete wavelet transform is used in a vast number of applications, the proposed algorithms can be utilized in those cases to achieve lossless, low-cost, and hardware-friendly architectures

Efficient architectures of heterogeneous fpga-gpu for 3-d medical image compression

The advent of development in three-dimensional (3-D) imaging modalities have generated a massive amount of volumetric data in 3-D images such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US). Existing survey reveals the presence of a huge gap for further research in exploiting reconfigurable computing for 3-D medical image compression. This research proposes an FPGA based co-processing solution to accelerate the mentioned medical imaging system. The HWT block implemented on the sbRIO-9632 FPGA board is Spartan 3 (XC3S2000) chip prototyping board. Analysis and performance evaluation of the 3-D images were been conducted. Furthermore, a novel architecture of context-based adaptive binary arithmetic coder (CABAC) is the advanced entropy coding tool employed by main and higher profiles of H.264/AVC. This research focuses on GPU implementation of CABAC and comparative study of discrete wavelet transform (DWT) and without DWT for 3-D medical image compression systems. Implementation results on MRI and CT images, showing GPU significantly outperforming single-threaded CPU implementation. Overall, CT and MRI modalities with DWT outperform in term of compression ratio, peak signal to noise ratio (PSNR) and latency compared with images without DWT process. For heterogeneous computing, MRI images with various sizes and format, such as JPEG and DICOM was implemented. Evaluation results are shown for each memory iteration, transfer sizes from GPU to CPU consuming more bandwidth or throughput. For size 786, 486 bytes JPEG format, both directions consumed bandwidth tend to balance. Bandwidth is relative to the transfer size, the larger sizing will take more latency and throughput. Next, OpenCL implementation for concurrent task via dedicated FPGA. Finding from implementation reveals, OpenCL on batch procession mode with AOC techniques offers substantial results where the amount of logic, area, register and memory increased proportionally to the number of batch. It is because of the kernel will copy the kernel block refer to batch number. Therefore memory bank increased periodically related to kernel block. It was found through comparative study that the tree balance and unroll loop architecture provides better achievement, in term of local memory, latency and throughput

New fast Walsh–Hadamard–Hartley transform algorithm

This paper presents an efficient fast Walsh–Hadamard–Hartley transform (FWHT) algorithm that incorporates the computation of the Walsh-Hadamard transform (WHT) with the discrete Hartley transform (DHT) into an orthogonal, unitary single fast transform possesses the block diagonal structure. The proposed algorithm is implemented in an integrated butterfly structure utilizing the sparse matrices factorization approach and the Kronecker (tensor) product technique, which proved a valuable and fast tool for developing and analyzing the proposed algorithm. The proposed approach was distinguished by ease of implementation and reduced computational complexity compared to previous algorithms, which were based on the concatenation of WHT and FHT by saving up to 3N-4 of real multiplication and 7.5N-10 of real addition

Modified Distributive Arithmetic based 2D-DWT for Hybrid (Neural Network-DWT) Image Compression

Artificial Neural Networks ANN is significantly used in signal and image processing techniques for pattern recognition and template matching Discrete Wavelet Transform DWT is combined with neural network to achieve higher compression if 2D data such as image Image compression using neural network and DWT have shown superior results over classical techniques with 70 higher compression and 20 improvement in Mean Square Error MSE Hardware complexity and power issipation are the major challenges that have been addressed in this work for VLSI implementation In this work modified distributive arithmetic DWT and multiplexer based DWT architecture are designed to reduce the computation complexity of hybrid architecture for image compression A 2D DWT architecture is designed with 1D DWT architecture and is implemented on FPGA that operates at 268 MHz consuming power less than 1

An Adaptive Threshold based FPGA Implementation for Object and Face detection

The moving object and face detection are vital requirement for real time security applications. In this paper, we propose an Adaptive Threshold based FPGA Implementation for Object and Face detection. The input Images and reference Images are preprocessed using Gaussian Filter to smoothen the high frequency components. The 2D-DWT is applied on Gaussian filter outputs and only LL bands are considered for further processing. The modified background with adaptive threshold are used to detect the object with LL band of reference image. The detected object is passed through Gaussian filter to enhance the quality of object. The matching unit is designed to recognize face from standard face database images. It is observed that the performance parameters such as percentage TSR and hardware utilizations are better compared to existing techniques