Architectural support for persistent memory systems

The long stated vision of persistent memory is set to be realized with the release of 3D XPoint memory by Intel and Micron. Persistent memory, as the name suggests, amalgamates the persistence (non-volatility) property of storage devices (like disks) with byte-addressability and low latency of memory. These properties of persistent memory coupled with its accessibility through the processor load/store interface enable programmers to design in-memory persistent data structures. An important challenge in designing persistent memory systems is to provide support for maintaining crash consistency of these in-memory data structures. Crash consistency is necessary to ensure the correct recovery of program state after a crash. Ordering is a primitive that can be used to design crash consistent programs. It provides guarantees on the order of updates to persistent memory. Atomicity can also be used to design crash consistent programs via two primitives. First, as an atomic durability primitive which guarantees that in the presence of system crashes updates are made durable atomically, which means either all or none of the updates are made durable. Second, in the form of ACID transactions that guarantee atomic visibility and atomic durability. Existing systems do not support ordering, let alone atomic durability or ACID. In fact, these systems implement various performance enhancing optimizations that deliberately reorder updates to memory. Moreover, software in these systems cannot explicitly control the movement of data from volatile cache to persistent memory. Therefore, any ordering requirement has to be enforced synchronously which degrades performance because program execution is stalled waiting for updates to reach persistent memory. This thesis aims to provide the design principles and efficient implementations for three crash consistency primitives: ordering, atomic durability and ACID transactions. A set of persistency models have been proposed recently which provide support for the ordering primitive. This thesis extends the taxonomy of these models by adding buffering, which allows the hardware to enforce ordering in the background, as a new layer of classification. It then goes on show how the existing implementation of a buffered model degenerates to a performance inefficient non-buffered model because of the presence of conflicts and proposes efficient solutions to eliminate or limit the impact of these conflicts with minimal hardware modifications. This thesis also proposes the first implementation of a buffered model for a server class processor with multi-banked caches and multiple memory controllers. Write ahead logging (WAL) is a commonly used approach to provide atomic durability. This thesis argues that existing implementations ofWAL in software are not only inefficient, because of the fine grained ordering dependencies, but also waste precious execution cycles to implement a fundamentally data movement task. It then proposes ATOM, a hardware log manager based on undo logging that performs the logging operation out of the critical path. This thesis presents the design principles behind ATOM and two techniques that optimize its performance. These techniques enable the memory controller to enforce fine grained ordering required for logging and to even perform logging in some cases. In doing so, ATOM significantly reduces processor stall cycles and improves performance. The most commonly used abstraction employed to atomically update persistent data is that of durable transactions with ACID (Atomicity, Consistency, Isolation and Durability) semantics that make updates within a transaction both visible and durable atomically. As a final contribution, this thesis tackles the problem of providing efficient support for durable transactions in hardware by integrating hardware support for atomic durability with hardware transactional memory (HTM). It proposes DHTM (durable hardware transactional memory) in which durability is considered as a first class design constraint. DHTM guarantees atomic durability via hardware redo-logging, and integrates this logging support with a commercial HTM to provide atomic visibility. Furthermore, DHTM leverages the same logging infrastructure to extend the supported transaction size, from being L1-limited to the LLC, with minor changes to the coherence protocol

Architectural Principles for Database Systems on Storage-Class Memory

Database systems have long been optimized to hide the higher latency of storage media, yielding complex persistence mechanisms. With the advent of large DRAM capacities, it became possible to keep a full copy of the data in DRAM. Systems that leverage this possibility, such as main-memory databases, keep two copies of the data in two different formats: one in main memory and the other one in storage. The two copies are kept synchronized using snapshotting and logging. This main-memory-centric architecture yields nearly two orders of magnitude faster analytical processing than traditional, disk-centric ones. The rise of Big Data emphasized the importance of such systems with an ever-increasing need for more main memory. However, DRAM is hitting its scalability limits: It is intrinsically hard to further increase its density. Storage-Class Memory (SCM) is a group of novel memory technologies that promise to alleviate DRAM’s scalability limits. They combine the non-volatility, density, and economic characteristics of storage media with the byte-addressability and a latency close to that of DRAM. Therefore, SCM can serve as persistent main memory, thereby bridging the gap between main memory and storage. In this dissertation, we explore the impact of SCM as persistent main memory on database systems. Assuming a hybrid SCM-DRAM hardware architecture, we propose a novel software architecture for database systems that places primary data in SCM and directly operates on it, eliminating the need for explicit IO. This architecture yields many benefits: First, it obviates the need to reload data from storage to main memory during recovery, as data is discovered and accessed directly in SCM. Second, it allows replacing the traditional logging infrastructure by fine-grained, cheap micro-logging at data-structure level. Third, secondary data can be stored in DRAM and reconstructed during recovery. Fourth, system runtime information can be stored in SCM to improve recovery time. Finally, the system may retain and continue in-flight transactions in case of system failures. However, SCM is no panacea as it raises unprecedented programming challenges. Given its byte-addressability and low latency, processors can access, read, modify, and persist data in SCM using load/store instructions at a CPU cache line granularity. The path from CPU registers to SCM is long and mostly volatile, including store buffers and CPU caches, leaving the programmer with little control over when data is persisted. Therefore, there is a need to enforce the order and durability of SCM writes using persistence primitives, such as cache line flushing instructions. This in turn creates new failure scenarios, such as missing or misplaced persistence primitives. We devise several building blocks to overcome these challenges. First, we identify the programming challenges of SCM and present a sound programming model that solves them. Then, we tackle memory management, as the first required building block to build a database system, by designing a highly scalable SCM allocator, named PAllocator, that fulfills the versatile needs of database systems. Thereafter, we propose the FPTree, a highly scalable hybrid SCM-DRAM persistent B+-Tree that bridges the gap between the performance of transient and persistent B+-Trees. Using these building blocks, we realize our envisioned database architecture in SOFORT, a hybrid SCM-DRAM columnar transactional engine. We propose an SCM-optimized MVCC scheme that eliminates write-ahead logging from the critical path of transactions. Since SCM -resident data is near-instantly available upon recovery, the new recovery bottleneck is rebuilding DRAM-based data. To alleviate this bottleneck, we propose a novel recovery technique that achieves nearly instant responsiveness of the database by accepting queries right after recovering SCM -based data, while rebuilding DRAM -based data in the background. Additionally, SCM brings new failure scenarios that existing testing tools cannot detect. Hence, we propose an online testing framework that is able to automatically simulate power failures and detect missing or misplaced persistence primitives. Finally, our proposed building blocks can serve to build more complex systems, paving the way for future database systems on SCM

Jiko kaifukugata operetingu shisutemu kochiku furemu waku

制度:新 ; 報告番号:甲2786号 ; 学位の種類:博士(工学) ; 授与年月日:2009/2/25 ; 早大学位記番号:新500

Redesigning Transaction Processing Systems for Non-Volatile Memory

Department of Computer Science and EngineeringTransaction Processing Systems are widely used because they make the user be able to manage their data more efficiently. However, they suffer performance bottleneck due to the redundant I/O for guaranteeing data consistency. In addition to the redundant I/O, slow storage device makes the performance more degraded. Leveraging non-volatile memory is one of the promising solutions the performance bottleneck in Transaction Processing Systems. However, since the I/O granularity of legacy storage devices and non-volatile memory is not equal, traditional Transaction Processing System cannot fully exploit the performance of persistent memory. The goal of this dissertation is to fully exploit non-volatile memory for improving the performance of Transaction Processing Systems. Write amplification between Transaction Processing System is pointed out as a performance bottleneck. As first approach, we redesigned Transaction Processing Systems to minimize the redundant I/O between the Transaction Processing Systems. We present LS-MVBT that integrates recovery information into the main database file to remove temporary files for recovery. The LS-MVBT also employs five optimizations to reduce the write traffics in single fsync() calls. We also exploit the persistent memory to reduce the performance bottleneck from slow storage devices. However, since the traditional recovery method is for slow storage devices, we develop byte-addressable differential logging, user-level heap manager, and transaction-aware persistence to fully exploit the persistent memory. To minimize the redundant I/O for guarantee data consistency, we present the failure-atomic slotted paging with persistent buffer cache. Redesigning indexing structure is the second approach to exploit the non-volatile memory fully. Since the B+-tree is originally designed for block granularity, It generates excessive I/O traffics in persistent memory. To mitigate this traffic, we develop cache line friendly B+-tree which aligns its node size to cache line size. It can minimize the write traffic. Moreover, with hardware transactional memory, it can update its single node atomically without any additional redundant I/O for guaranteeing data consistency. It can also adapt Failure-Atomic Shift and Failure-Atomic In-place Rebalancing to eliminate unnecessary I/O. Furthermore, We improved the persistent memory manager that exploit traditional memory heap structure with free-list instead of segregated lists for small memory allocations to minimize the memory allocation overhead. Our performance evaluation shows that our improved version that consider I/O granularity of non-volatile memory can efficiently reduce the redundant I/O traffic and improve the performance by large of a margin.ope

FPTree: A Hybrid SCM-DRAM Persistent and Concurrent B-Tree for Storage Class Memory

The advent of Storage Class Memory (SCM) is driving a rethink of storage systems towards a single-level architecture where memory and storage are merged. In this context, several works have investigated how to design persistent trees in SCM as a fundamental building block for these novel systems. However, these trees are significantly slower than DRAM-based counterparts since trees are latency-sensitive and SCM exhibits higher latencies than DRAM. In this paper we propose a novel hybrid SCM-DRAM persistent and concurrent B-Tree, named Fingerprinting Persistent Tree (FPTree) that achieves similar performance to DRAM-based counterparts. In this novel design, leaf nodes are persisted in SCM while inner nodes are placed in DRAM and rebuilt upon recovery. The FPTree uses Fingerprinting, a technique that limits the expected number of in-leaf probed keys to one. In addition, we propose a hybrid concurrency scheme for the FPTree that is partially based on Hardware Transactional Memory. We conduct a thorough performance evaluation and show that the FPTree outperforms state-of-the-art persistent trees with different SCM latencies by up to a factor of 8.2. Moreover, we show that the FPTree scales very well on a machine with 88 logical cores. Finally, we integrate the evaluated trees in memcached and a prototype database. We show that the FPTree incurs an almost negligible performance overhead over using fully transient data structures, while significantly outperforming other persistent trees

In vitro expanded human CD4+CD25+ regulatory T cells suppress effector T cell proliferation.

Regulatory T cells (Tregs) have been shown to be critical in the balance between autoimmunity and tolerance and have been implicated in several human autoimmune diseases. However, the small number of Tregs in peripheral blood limits their therapeutic potential. Therefore, we developed a protocol that would allow for the expansion of Tregs while retaining their suppressive activity. We isolated CD4+CD25 hi cells from human peripheral blood and expanded them in vitro in the presence of anti-CD3 and anti-CD28 magnetic Xcyte Dynabeads and high concentrations of exogenous Interleukin (IL)-2. Tregs were effectively expanded up to 200-fold while maintaining surface expression of CD25 and other markers of Tregs: CD62L, HLA-DR, CCR6, and FOXP3. The expanded Tregs suppressed proliferation and cytokine secretion of responder PBMCs in co-cultures stimulated with anti-CD3 or alloantigen. Treg expansion is a critical first step before consideration of Tregs as a therapeutic intervention in patients with autoimmune or graft-versus-host disease

Virtual workplaces : when metaphors breakdown

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1998.Includes bibliographical references (leaves 79-81).Our model of work is shaped by the places we choose to work and the tools we choose to work with. As we introduce new technologies and build new environments our model is changing. Today's virtual workplaces are grounded in models of work that have been reformed from our experiences using current technology in physical workspace. However we are discovering opportunities and possibilities for work in collaborative, virtual environments that question physical models. Emerging patterns of distributed collaboration in persistent virtual environments are changing the way we work in time and space, recasting our notion of workplace. Virtual workplaces are interpreted and experienced through metaphors that describe a space of potential for work occurrences. Through the lens of metaphors, this research focuses on breakdowns between collaborative work and the environment in which work occurs. If what we understand and predict is based on what we already know, then by examining the breakdowns between design and use of collaborative environments we can illuminate the space of possibilities for collaborative work.by Thomas W.I. Gallemore.M.S

Evaluation of two mutants of \u3ci\u3eMycobacterium avium\u3c/i\u3e subsp. \u3ci\u3eparatuberculosis\u3c/i\u3e as candidates for a live attenuated vaccine for Johne’s disease

Control of Johne’s disease, caused by Mycobacterium avium subsp. paratuberculosis, has been difficult because of a lack of an effective vaccine. To address this problem we used targeted gene disruption to develop candidate mutants with impaired capacity to survive ex vivo and in vivo to test as a vaccine. We selected relA and pknG, genes known to be important virulence factors in Mycobacterium tuberculosis and Mycobacterium bovis, for initial studies. Deletion mutants were made in a wild type Map (K10) and its recombinant strain expressing the green fluorescent protein (K10-GFP). Comparison of survival in an ex vivo assay revealed deletion of either gene attenuated survival in monocyte-derived macrophages compared to survival of wild-type K10. In contrast, study in calves revealed survival in vivo was mainly affected by deletion of relA. Bacteria were detected in tissues from wild-type and the pknG mutant infected calves by bacterial culture and PCR at three months post infection. No bacteria were detected in tissues from calves infected with the relA mutant (P \u3c 0.05). Flow cytometric analysis of the immune response to the wild-type K10-GFP and the mutant strains showed deletion of either gene did not affect their capacity to elicit a strong proliferative response to soluble antigen extract or live Map. Quantitative RTPCR revealed genes encoding IFN-ƴ, IL-17, IL-22, T-bet, RORC, and granulysin were up-regulated in PBMC stimulated with live Map three months post infection compared to the response of PBMC pre-infection. A challenge study in kid goats showed deletion of pknG did not interfere with establishment of an infection. As in calves, deletion of relA attenuated survival in vivo. The mutant also elicited an immune response that limited colonization by challenge wild type Map. The findings show the relA mutant is a good candidate for development of a live attenuated vaccine for Johne’s disease

Changing practice in dementia care in the community: developing and testing evidence-based interventions, from timely diagnosis to end of life (EVIDEM)

Background Dementia has an enormous impact on the lives of individuals and families, and on health and social services, and this will increase as the population ages. The needs of people with dementia and their carers for information and support are inadequately addressed at all key points in the illness trajectory. Methods The Unit is working specifically on an evaluation of the impact of the Mental Capacity Act 2005, and will develop practice guidance to enhance concordance with the Act. Phase One of the study has involved baseline interviews with practitioners across a wide range of services to establish knowledge and expectations of the Act, and to consider change processes when new policy and legislation are implemented. Findings Phase 1, involving baseline interviews with 115 practitioners, identified variable knowledge and understanding about the principles of the Act. Phase 2 is exploring everyday decision-making by people with memory problems and their carers